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hot swap controller and digital power and energy monitor with pmbus interface data sheet adm1278 features 0.3% accurate, 12 - bit adc for i out , v in , v out , and temperature 320 ns response time to short circuit shutdown on detection of fet health fault constant power foldback for tighter fet soa protection remote temperature sensing with programmable warning and shutdown thresholds resistor - programmable 5 mv to 25 mv v sense current limit programmable start - up current limit 1% accurate uv , ov , and p wrgd thresholds split hot swap an d power monitor inputs to allow additional external adc filtering reports power and energy consumption over time peak detect registers for current, voltage, and power prochot power throttling capability pmbus fast mode compliant interface 5 mm 5 mm, 32 - l ead lfcsp applications servers power monitoring and control/power budgeting telecommunication and data communication equipment typical application circuit gate q 1 mo+ hs+ hs? timer timer adm1278-1 mo? r sense 4.5v t o 20v vcc v cp vcap i sense uv ov 1.0v 1.0v temp vout pwgin 1.0v v out 12-bit adc scl sda adr2 i sense hs+ temp ldo charge pump timeout i out gpo1/alert1/conv enable gpo2/alert2 v cbos istart iset pset timeout current- limit control ref select 1.0v hs? fault retry pwrgd adr1 csout gate drive/ logic logic and pmbus analog vout 50 + + + + ? ? ? ? + ? gnd pgnd 12198-001 figure 1. general description the adm1278 is a hot swap controller that allows a circuit board to be removed from or inserted into a live backplane. it also features current, voltage, power , and temperature readback via an integrated 12- bit analog - to - digital converter (adc), accessed using a pmbus? interface. the load current is measured using an internal current sense amplifier that measure s the voltage across a sense resistor in the power path via the hs+ and hs ? pins. a default current limit of 20 mv is set, but this limit can be adjusted, if required. the adm1278 limits the cur rent through the sense resistor by controlling the gate voltage of an external n - channel fet in the power path, via the gate pin. the sense voltage, and therefore the load current, is maintained below the preset maximum. the adm1278 protects the external fet by limiting the time that the fet remains on while the current is at its maximum value. this current - limit time is set by the choice of capacitor connected to the timer pin. in addition, a co nstant power foldback scheme is used to control the power dissipation in the mosfet during power - up and fault conditions. the level of this power, along with the timer regulation time, can be set to ensure tha t the mosfet remains within safe operating area (soa) limits. in case of a short - circuit event, a fast internal overcurrent detector responds within 320 ns and signals the gate to shut down. a 1500 ma pull - down device ensures a fast fet response. the adm1278 features overvoltage (ov) and undervoltage (uv) protection, programmed using external resistor dividers on the uv and ov pins. a pwrgd signal can be used to detect when the output supply is valid, using the pwgin pin to accurately monitor the output. the adm1278 is available in a 32 - lead lfcsp with a retry pi n that can be configure d for automatic retry or latch - off wh en an overcurrent fault occurs. table 1 . model options model adc accuracy spi interface enable pin 1 adm1278 - 1aa 0.3% no active h igh adm1278 - 1a 0.7% no active h igh adm1278 - 1b 1.0% no active h igh adm1278 - 2a 0.7% yes active h igh adm1278 - 3a 0.7% no active l ow 1 active high relates to the enable p in, and active low r elates to the enable pin. rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com
adm1278 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 ge neral description ......................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 power monitoring accuracy specifications .............................. 8 serial bus timing characteristics .............................................. 8 spi timing characteristics (adm1278 - 2) ............................... 9 absolute maximum ratings .......................................................... 10 thermal characteristics ............................................................ 10 esd caution ................................................................................ 10 pin configurations and function descriptions ......................... 11 typical performance characteristics ........................................... 17 theory of operation ...................................................................... 24 powering the adm1278 ............................................................ 24 hot swap current sense inputs ................................................ 24 power monitor current sense inputs ...................................... 25 current - limit reference ........................................................... 25 sett ing the current limit (iset) .............................................. 26 setting a linear output voltage ramp at power - up ............. 26 start - up current limit .............................................................. 27 constant power foldback .......................................................... 28 time r ............................................................................................ 28 hot swap retry ........................................................................... 29 fet gate drive clamps ............................................................. 29 fast response to severe overcurrent ...................................... 29 undervoltage and overvoltage ................................................. 29 power good ................................................................................. 29 fault pin ................................................................................... 29 enable/ enable input .......................................................... 30 current sense output (csout) .............................................. 30 remote temperature sensing ................................................... 30 spi interface ................................................................................ 31 v out measurement ..................................................................... 32 fet health .................................................................................. 32 power throttling ......................................................................... 32 power monito r ............................................................................ 32 pmbus interface ............................................................................. 34 device addressing ...................................................................... 34 smbus protocol usage ............................................................... 34 packet error checking ............................................................... 34 partia l transactions on i 2 c bus ................................................ 35 smbus message formats ........................................................... 35 group commands ..................................................................... 37 hot swap control commands ................................................. 37 ad m1278 information commands ........................................ 37 status commands ...................................................................... 38 gpo and alert pin setup commands ..................................... 38 power monitor commands ...................................................... 39 warning limit setup commands ............................................ 40 pmbus direct format conversion .......................................... 40 voltage and current conversion using lsb values .............. 41 alert pin behavior .......................................................................... 42 faults and warnings .................................................................. 42 generating an alert ................................................................... 42 handling/clearing an alert ...................................................... 42 smbus alert response addre ss ............................................... 43 example use of smbus ara .................................................... 43 digital comparator mode ......................................................... 43 typical application circuits ..................................................... 43 pmbus command reference ........................................................ 45 register details ............................................................................... 46 operation register ..................................................................... 46 clear faults register .................................................................. 46 pmbus capability register ....................................................... 46 v out ov warning limit register ............................................. 46 v out uv warnin g limit register ............................................. 47 i out oc warning limit register .............................................. 47 ot fault limit register ............................................................. 47 ot w arning limit register ...................................................... 47 v in ov warning limit register ............................................... 47 v in uv warning limit register ............................................... 48 p in op warning limit register ................................................ 48 status byte register .................................................................... 48 status word register .................................................................. 49 v out status register ................................................................... 50 i out status register ..................................................................... 50 input st atus register .................................................................. 50 temperature status register ..................................................... 51 rev. a | page 2 of 61
data sheet adm1278 manufacturer specific status register ...................................... 51 read e in register ......................................................................... 52 read v in r egister ........................................................................ 52 read v out register ...................................................................... 53 read i out register ....................................................................... 53 read temperature 1 register ..................................................... 53 read p in register ......................................................................... 53 pmbus revision register ........................................................... 53 manufacturer id register .......................................................... 54 manufacturer model register .................................................... 54 manufacturer revision register ................................................ 54 manufacturer date register ....................................................... 54 peak i out register ........................................................................ 54 peak v in register ......................................................................... 55 peak v out register ...................................................................... 55 power monitor control register ............................................... 55 power monitor configuration register ................................... 55 alert 1 configuration register .................................................. 56 alert 2 configuration register .................................................. 57 peak temperature register ........................................................ 57 device configuration register .................................................. 57 power cycle register .................................................................. 58 peak p in register ......................................................................... 59 read p in (extended) register .................................................... 59 read e in (extended) register .................................................... 59 hysteresis low level register ................................................... 59 hysteresis high level register .................................................. 59 hysteresis status register ........................................................... 60 st art - up i out limit register ...................................................... 60 outline dimensions ........................................................................ 61 ordering guide ........................................................................... 61 revision history 12 /14 rev. 0 to rev. a changes to features section, general description section, and applications section .................................................................. 1 added table 1, renumbered sequentially ..................................... 1 change s to power_cycle command section ...................... 37 change to power cycle register section ...................................... 58 6/14 revision 0: initial version rev. a | page 3 of 61
adm1278 data sheet specifications v cc = 4.5 v to 20 v, v cc v hs+ and v mo+ , v hs+ = 2 v to 20 v, v sense_hs = (v hs+ ? v hs? ) = 0 v, t a = ?40c to +85c, unless otherwise noted. t able 2 . parameter 1 symbol min typ max unit test conditions/comments power supply operating voltage range v cc 4.5 20 v undervoltage lockout uvlo 2.4 2.7 v v cc rising undervoltage hysteresis 90 120 mv quiescent current i cc 5.5 ma gate on and power monitor running uv pin input current i uv 50 na uv 3.6 v uv threshold uv th a grade and aa grade 0.99 1.0 1.01 v uv falling b grade only 0.97 1.0 1.03 v uv falling uv threshold hysteresis uv hyst 45 60 75 mv uv glitch filter uv gf 2 7 s 50 mv overdrive uv propagation delay uv pd 5 8 s uv low to gate pull - down active ov pin input current i ov 50 na ov 3.6 v ov threshold ov th a grade and aa grade 0.99 1.0 1.01 v ov rising b grade only 0.97 1.0 1.03 v ov rising ov threshold hysteresis ov hyst 45 60 75 mv ov glitch filter ov gf 1.5 3.5 s 50 mv overdrive ov propagation delay ov pd 3.0 4.0 s ov high to gate pull - down active hs+ and hs? pins input current i sensex 150 a per individual pin; v hs+ , v hs? = 20 v input imbalance i sense 5 a i sense = (i + ? i ? ) mo+ and mo? pins input current i mo 25 na per individual pin; v mo+ , v mo? = 20 v vcap pin internally regulated voltage v vcap a grade and aa grade 2.68 2.7 2.72 v 0 a i vcap 100 a; c vcap = 1 f b grade only 2.66 2.7 2.74 v 0 a i vcap 100 a; c vcap = 1 f iset pin reference select threshold v isetrsth 1.35 1.5 1.65 v if v iset > v isetrsth , an internal 1 v reference (v clref ) is used internal reference v clref 1 v accuracies included in total sense voltage accuracies gain of current sense amplifier av csamp 50 v/v accuracies included in total sense voltage accuracies recommended maximum operating range v iset 0.25 1.25 v 5 mv to 25 mv v sense current limit input current i iset 100 na v iset v vcap gate pin maximum voltage on the gate is always clamped to 31 v gate drive voltage v gate v gate = v gate ? v out 10 12 14 v 20 v v cc 8 v; i gate 5 a 8 10 v v hs+ = v cc = 5 v; i gate 5 a 7 9 v v hs+ = v cc = 4.5 v; i gate 1 a gate pull - up current i gateup ?20 ?30 a v gate = 0 v gate pull - down current i gatedn regulation i gatedn_reg 45 60 75 a v gate 2 v; v iset = 1.0 v; ( v hs+ ? v hs? ) = 30 mv slow i gatedn_slow 5 10 15 ma v gate 2 v fast i gatedn_fast 750 1500 2250 ma v gate 12 v; v cc 12 v gate holdoff resistance 20 ? v cc = 0 v, v gate = 2 v rev. a | page 4 of 61
data sheet adm1278 parameter 1 symbol min typ max unit test conditions/comments hot swap sense voltage hot swap sense voltage current limit v sensecl a grade and aa grade 19.75 20 20.25 mv v iset > 1.65 v; v gate = (v hs+ + 3 v); i gate = 0 a b grade only 19.6 20 20.4 mv v iset > 1.65 v; v gate = (v hs+ + 3 v); i gate = 0 a constant power inactive v gate = (v hs+ + 3 v); i gate = 0 a; v ds = (hs?) ? v out a grade and aa grade 24.75 25 25.25 mv v iset = 1.25 v; v ds < 2 v 19.75 20 20.25 mv v iset = 1.0 v; v ds < 2 v 14.75 15 15.25 mv v iset = 0.75 v; v ds < 2 v b grade only 24.6 25 25.4 mv v iset = 1.25 v; v ds < 2 v 19.6 20 20.4 mv v iset = 1.0 v; v ds < 2 v 14.6 15 15.4 mv v iset = 0.75 v; v ds < 2v constant power active fet power limit = (v pset 8)/(50 r sense ); constant power active when v ds > (v pset 8)/i set a grade and aa grade 9.25 10 10.75 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 4 v 4.65 5 5.35 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 8 v 1.7 2 2.3 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 20 v b grade only 9 10 11 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 4 v 4.6 5 5.4 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 8 v 1.4 2 2.6 mv v iset > 1.65 v; v pset = 0.25 v; v ds = 20 v start - up current limit v istartcl a grade and aa grade 4.7 5 5.3 mv strt_up_iout_lim = 3; v iset > 1.65 v 3.7 4 4.3 mv v istart = 0.2 v b grade only 4.5 5 5.5 mv strt_up_iout_lim = 3; v iset > 1.65 v 3.5 4 4.5 mv v istart = 0.2 v start - up current - limit clamp v istartcl_clamp a grade and aa grade 1.6 2 2.4 mv v istart = 0 v or strt_up_iout_lim = 0 b grade only 1.4 2 2.6 mv v istart = 0 v or strt_up_iout_lim = 0 circuit breaker offset v cbos 0.6 0.88 1.12 mv circuit breaker trip voltage, v cb = v sensecl ? v cbos severe overcurrent voltage threshold v senseoc a grade and aa grade 23 25 27 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (125%) 28 30 32 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (150%) 38 40 42 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (200%) 43 45 47 mv v iset > 1.65 v; v pset > 1.1 v; default at power - up (225%) b grade only 20 25 30 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (125%) 25 30 35 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (150%) 35 40 45 mv v iset > 1.65 v; v pset > 1.1 v; optional select pmbus (200%) 40 45 50 mv v iset > 1.65 v; v pset > 1.1 v; default at power - up (225%) short glitch filter duration 100 220 ns v sense_hs step = 18 mv to (2 mv above v senseoc_max ) long glitch filter duration (default) 530 900 ns v sense_hs step = 18 mv to (2 mv above v senseoc_max ) response time short glitch filter 200 320 ns v sense_hs step = 18 mv to (2 mv above v senseoc_max ) long glitch filter 630 1000 ns v sense_hs step = 18 mv to (2 mv above v senseoc_max ) istart pin active range 0.1 1.25 v tie istart to vcap to disable start - up current limit gain of current sense amplifier av csamp 50 v/v accuracies included in total sense voltage accuracies input current i istart 100 na v istart v vcap timer pin timer pull - up current power - on reset (por) i timeruppor ?2 ?3 ?4 a initial power - on reset; v timer = 0.5 v overcurrent (oc) fault i ti meru pflt ?57 ?60 ?63 a overcurrent fault; 0.2 v v timer 1 v rev. a | page 5 of 61
adm1278 data sheet parameter 1 symbol min typ max unit test conditions/comments timer pull - down current retry i timerdnrt 1.7 2 2.3 a after fault when gate is off; v timer = 0.5 v hold i timerdnhold 100 a holds timer at 0 v when inactive; v timer = 0.5 v timer high threshold v timerh 0.98 1.0 1.02 v timer low threshold v timerl 0.18 0.2 0.22 v timer glitch filter timer gf 10 s minimum por duration 27 ms minimum initial insertion delay regardless of c timer value pset pin fet power limit = (v pset 8)/(50 r sense ) reference select threshold v psetrsth 1.35 1.5 1.65 v if v pset > v psetrsth , constant power is disabled gain of current sense amplifier av csamp 50 v/v accuracies included in total sense voltage accuracies input current i pset 100 na v pset v vcap vout pin input current 40 a v out = 20 v fau lt pin output low voltage v ol_latch 0.4 v i fau lt = 1 ma 1.5 v i fau lt = 5 ma leakage current 100 na v fau lt 2 v ; fau lt ou tput high -z 1 a v fau lt = 20 v; fau lt outp ut high -z enable pin input high voltage v ih 1.1 v input low voltage v il 0.8 v glitch filter 1 s retry pin input high voltage v ih 1.1 v latch off when high; internal pull - up sets this as default input low voltage v il 0.8 v 10 second automatic retry when pin pulled low glitch filter 1 s internal pull - up current 8 a csout pin csout gain 350 v/v csout = v sense_hs 350; vcc > csout + 2 v total output error ?1.6 +1.6 % v sense_hs = 20 mv; i csout 1 ma; c csout = 1 nf ?3.0 +3.0 % v sense_hs = 10 mv; i csout 1 ma; c csout = 1 nf output swing to gnd 40 mv current limiting 5 ma csout short - circuit current gpo1 / alert1 / conv pin output low voltage v ol_gpo1 0.4 v i gpo1 = 1 ma 1.5 v i gpo1 = 5 ma leakage current 100 na v gpo1 2 v; gpo1 output high -z 1 a v gpo1 = 20 v; gpo1 output high -z input high voltage v ih 1.1 v configured as conv input low voltage v il 0.8 v configured as conv glitch filter 1 s configured as conv gp o2/ alert2 pin output low voltage v ol_gpo2 0.4 v i gpo2 = 1 ma 1.5 v i gpo2 = 5 ma leakage current 100 na v gpo2 2 v; gpo2 output high -z 1 a v gpo2 = 20 v; gpo2 output high -z pwrgd pin output low voltage v ol_pwrgd 0.4 v i pwrgd = 1 ma 1.5 v i pwrgd = 5 ma vcc that guarantees valid output 1 v i sink = 100 a; v ol_pwrgd = 0.4 v leakage current 100 na v pwrgd 2 v; pwrgd output high -z 1 a v pwrgd = 20 v; pwrgd output high - z rev. a | page 6 of 61
data sheet adm1278 parameter 1 symbol min typ max unit test conditions/comments pwgin pin input current i pwgin 50 na pwgin 3.6 v pwgin threshold pwgin th a grade and aa grade 0.99 1.0 1.01 v pwgin falling b grade only 0.97 1.0 1.03 v pwgin falling pwgin threshold hysteresis pwgin hyst 50 60 70 mv glitch filter 1 s asserting and deasserting of pwrgd pin current and voltage monitoring see table 3 for power monitor accuracy specifications adc conversion time includes time for power multiplication 144 165 s one sample of i out ; from command received to valid data in register 64 73 s one sample of v in ; from command received to valid data in register 64 73 s one sample of v out ; from command received to valid data in register adrx pins address set to 00 0 0.8 v connect to gnd input current for address set to 00 ?40 ?22 a v adr x = 0 v to 0.8 v address set to 01 135 150 165 k? resistor to gnd address set to 10 ?1 +1 a no connect state; maximum leakage current allowed address set to 11 2 v connect to vcap input current for address set to 11 3 10 a v adr x = 2.0 v to vcap; must not exceed the maximum allowable current draw from vcap temp pin external transistor is 2n3904 operating range ?55 +150 c limited by external diode accuracy 1 10 c t a = t diode = ?40c to +85c resolution 0.25 c
adm1278 data sheet rev. a | page 8 of 61 parameter 1 symbol min typ max unit test conditions/comments nominal bus voltage v dd 2.7 5.5 v 3 v to 5 v 10% capacitance for sda, scl pins c pin 5 pf input glitch filter t sp 0 50 ns 1 dual function pin names are referenced by the relevant function only (see the pin configurations and funct ion descriptions sec tion for full pin mnemonics and descriptions). 2 sampled during initial release to ensure compliance, but not subject to production testing. power monitoring accuracy specifications table 3. aa grade a grade b grade parameter min typ max min typ max min typ max unit test conditions/comments current and voltage monitoring current sense absolute error v cc = 4.5 v to 15 v; v mo+ = 2 v to 15 v, 128-sample averaging (unless otherwise noted) 0.25 0.7 1.0 % v sense_mo = 25 mv 0.04 0.3 0.04 0.7 1.0 % v sense_mo = 20 mv 0.5 1.0 1.5 % v sense_mo = 20 mv; 16-sample averaging 1.5 2.8 4.0 % v sense_mo = 20 mv; one-sample averaging 0.3 0.8 1.1 % v sense_mo = 15 mv 0.4 1.1 1.5 % v sense_mo = 10 mv 0.75 2.0 3.0 % v sense_mo = 5 mv 1.6 4.3 6.2 % v sense_mo = 2.5 mv hs+/vout absolute error 0.35 1.0 1.5 % v hs+ , v out = 10 v to 20 v 0.5 1.0 1.5 % v hs+ , v out = 5 v power absolute error 0.65 1.7 2.5 % v sense_mo = 20 mv, v hs+ = 12 v serial bus timing characteristics table 4. parameter description min typ max unit f sclk clock frequency 400 khz t buf bus free time 1.3 s t hd;sta start hold time 0.6 s t su;sta start setup time 0.6 s t su;sto stop setup time 0.6 s t hd;dat sda hold time 300 900 ns t su;dat sda setup time 100 ns t low scl low time 1.3 s t high scl high time 0.6 s t r 1 scl, sda rise time 20 300 ns t f 1 scl, sda fall time 20 300 ns 1 t r = (v il(max) ? 0.15) to (v ih3v3 + 0.15) and t f = 0.9 v dd to (v il(max) ? 0.15); where v ih3v3 = 2.1 v, and v dd = 3.3 v. v ih3v3 is the input high voltage when v dd = 3.3 v.
data sheet adm1278 rev. a | page 9 of 61 t low t buf t hd;dat t su;dat t su;sta t hd;sta t high t r t f t su;sto p s s p v ih v il v ih v il scl sda 12198-002 figure 2. serial bus timing diagram spi timing characteristics ( adm1278-2 ) table 5. parameter description min typ max unit test conditions/comments t s 1 spi_ss falling edge to mclk rising edge setup time 50 ns t high 1 mclk high time 180 ns t low 1 mclk low time 180 ns t clk 1 mclk cycle time 1 s t h 1 hold time between spi_ss and mclk 1 s t v hold time between new data valid and mclk falling edge 110 260 ns track capacitance = 120 pf; i ol = 4 ma t on spi_ss falling edge to mdat active time 130 240 ns track capacitance = 120 pf; i ol = 4 ma t off bus relinquish time after spi_ss rising edge 130 280 ns track capacitance = 120 pf; i ol = 4 ma 1 guaranteed by design, but not production tested. spi_ss mclk mdat t s 1 79 78 msb lsb 23 t high t low t on don?t care t clk t h t off t v don?t care 12198-003 figure 3. spi timing diagram
adm1278 data sheet absolute maximum rat ings table 6 . parameter rating vcc pin ?0.3 v to +25 v uv pin ?0.3 v to +4 v ov pin ?0.3 v to +4 v istart pin ?0.3 v to +4 v timer pin ?0.3 v to vcap + 0.3 v temp pin ?0.3 v to vcap + 0.3 v vcap pin ?0.3 v to +4 v iset pin ?0.3 v to +4 v pset pin ?0.3 v to +4 v fau lt pi n ?0.3 v to +25 v retry pin ?0.3 v to +4 v pwgin pin ?0.3 v to +4 v scl pin ?0.3 v to +6.5 v sda pin ?0.3 v to +6.5 v spi_ss pin ?0.3 v to +4 v mclk pin ?0.3 v to +4 v mdat pin ?0.3 v to +4 v adr1 pin ?0.3 v to +6.5 v adr2 pin ?0.3 v to +6.5 v enable pin ?0.3 v to +25 v gp o1/ alert1 /con v pin ?0.3 v to +25 v gpo 2/ alert2 pi n ?0.3 v to +25 v pwrgd pin ?0.3 v to +25 v vout pin ?0.3 v to +25 v gate pin (internal supply only) 1 ?0.3 v to +36 v hs+ pin ?0.3 v to +25 v hs? pin ?0.3 v to +25 v mo+ pin ?0.3 v to +25 v mo? pin ?0.3 v to +25 v pgnd 0.3 v v sense_hs (v hs+ ? v hs? ) 0.3 v v sense_mo (v mo+ ? v mo? ) 0.3 v csout shor t - circuit duration indefinite continuous current into any pin 10 ma storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature, soldering (10 sec) 300c junction temperature 105c 1 the gate pin has internal clamping circuits to prevent the gate pin voltage from exceeding the maximum ratings of a mosfet with gain to source voltage, v gsmax = 20 v, and internal process limits. applying a voltage source to this pin externally may cause irreversible damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in th e operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characterist ics ja is specified for the worst - case conditions, that is, a device sol dered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja unit 32- lead lfcsp (cp -32-13) 32.5 c/w esd caution rev. a | page 10 of 61
data sheet adm1278 pin configurations a nd function descript ions notes 1. nic = not internally connected. 2. solder the exposed pad to the board to improve thermal dissipation. the exposed pad can be connected to ground. 1 pset 2 vca p 3 iset 4 is t art 5 timer 6 f au l t 7 adr1 8 adr2 24 ga te 23 pgnd 22 gnd 21 pwgin 20 vout 19 csout 18 pwrgd 17 ret r y 9 nic 10 nic 1 1 nic 12 enable 13 gpo1/alert1/conv 14 gpo2/alert2 15 sda 16 scl 32 ov 31 uv 30 vcc 29 mo+ 28 hs+ 27 hs? 26 mo? 25 tem p adm1278-1 t op view (not to scale) 12198-004 figure 4. adm1278 - 1 pin configuration 1 pset 2 vca p 3 iset 4 is t art 5 timer 6 f au l t 7 adr1 8 adr2 24 g a te 23 pgnd 22 gnd 21 pwgin 20 vout 19 csout 18 pwrgd 17 ret r y 9 nic 10 nic 1 1 nic 12 enable 13 gpo1/alert1/conv 14 gpo2/alert2 15 sda 16 scl 32 ov 31 uv 30 vcc 29 mo+ 28 hs+ 27 hs? 26 mo? 25 tem p adm1278-3 t o p view (not to scale) 12198-106 notes 1. nic = not internally connected. 2. solder the exposed pad to the board to improve thermal dissipation. the exposed pad can be connected to ground. figure 5. adm1278 - 3 pin configuration table 8 . adm1278 - 1 and adm1278 -3 pin function descriptions mnemonic pin no. adm1278 - 1 adm1278 - 3 description 1 pset pset power limit. this pin allows the constant power limit to be programmed. the current limit is dynamically adjusted to ensure that the maximum power dissipation in the fet never exceeds this limit during any operating condition. the power limit can be adjusted to a user defined value using a resistor divider from vcap. an external reference can also be used. the fet power is limited to (v pset 8)/(50 r sense ). 2 vcap vcap internal regulated supply. place a capacitor with a value of 1 f or greater on this pin to maintain accuracy. this pin can be used as a reference to program the iset pin voltage. 3 iset iset current limit. this pin allows the current - limit thre shold to be programmed. the default limit is set when this pin is connected directly to vcap. to achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from vcap. an external reference can also be used. 4 istart i start start - up current limit. this pin allows a separate start - up current limit to be set for dv/dt power - up mode. when powering up in dv/dt mode, the current charging the capacitor is constant and is typically much smaller than the normal load current. th e istart pin sets the start - up current limit in a similar manner as iset is used to set the normal current limit. the start - up current limit is only active while pwrgd is low. the start - up current limit can also be set over pmbus with the strt_up_iout_lim register. start - up current limit = v iset (strt_up_iout_lim/16). the lowest of all the active current limits always takes priority. 5 timer timer timer. an external capacitor, c timer , sets an initial timing cycle delay and a fault delay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 6 fau lt fau lt fault. this pin asserts low and latches after a fault has occurred. the faults that can trigger this pin include an overcurrent fau lt resulting in the timer pin voltage exceeding the upper threshold, an overtemperature fault, and an fet health fault. this is an open - drain output pin. 7, 8 adr1, adr2 adr1, adr2 pmbus address. these pins can be tied to gnd, tied to vcap, left floating, or tied low through a resistor for a total of 16 unique pmbus device addresses (see the device addressing section). 9, 10, 11 nic nic not internally connected. rev. a | page 11 of 61
adm1278 data sheet rev. a | page 12 of 61 mnemonic pin no. adm1278-1 adm1278-3 description 12 enable enable enable. on the adm1278-1 , the enable pin is an active high digital input pin. this input must be high to allow the adm1278-1 hot swap controller to begin a power-up sequence. if the enable pin is held low, the adm1278-1 is prevented from initiating a hot swap attempt. on the adm1278-3 , the enable pin is an active low digital input pin. this input must be low to allow the adm1278-3 hot swap controller to begin a power-up sequence. if the enable pin is held high, the adm1278-3 is prevented from initiating a hot swap attempt. 13 gpo1/alert1 / conv gpo1/alert1 / conv general-purpose digital output (gpo1). alert (alert1 ).this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. conversion (conv). this pin can be used as an input signal to control when a power monitor adc sampling cycle begins. the gpo1/alert1 /conv pin defaults to an alert output at power-up. this is an open-drain output pin. 14 gpo2/alert2 gpo2/alert2 general-purpose digital output (gpo2). alert (alert2 ). this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. the gpo2/alert2 pin defaults to an alert output at power-up. this is an open-drain output pin. 15 sda sda serial data input/output. open-d rain input/output. requires an external pull-up resistor. if the i 2 c pins, sda and scl, are not used, tie them to gnd or via a resistor pull-up to vcap or another supply. this avoids any glitches on the i 2 c pins being interpreted as i 2 c transactions. 16 scl scl serial clock. open-drain input. requires an external pull-up resistor. if the i 2 c pins, sda and scl, are not used, tie them to gnd or via a pu ll-up resistor to vcap or another supply. this avoids any glitches on the i 2 c pins being interpreted as i 2 c transactions. 17 retry retry retry. the retry pin has an internal pull-up resistor; therefore, it can be left floating to enable the default latch off mode after an overcurrent fault. this pin can be pulled low to enable a 10 second autoretry following an overcurrent fault. 18 pwrgd pwrgd power-good signal. this pin indicates that the supply is within tolerance (pwgin input), no faults have been detected, and the adm1278-1 hot swap is enabled with the gate fully enhanced. this is an open-drain output pin. 19 csout csout current sense output. the v sense_hs voltage is amplified to give an output voltage corresponding to the load current. 20 vout vout output voltage. vout is an input pin and is used to read back the output voltage using the internal adc. insert a 1 k resistor in series between the source of a fet and the vout pin. this pin is also used along with hs? to calculate the drain to source voltage (v ds ) of the fet for constant power foldback operation. 21 pwgin pwgin power-good input. this pin sets the power-good input threshold. the user can set an accurate power-good threshold with a resistor divider fr om the source of the fet (vout). the pwrgd output signal is no t asserted high until the output voltag e is above the threshold set by this pin. 22 gnd gnd ground. this pin is the ground connection for all of the sensitive analog nodes. take care to isolate this ground connection from the main high current path and any large transients. a good technique for this is to create a ground island around the adm1278-1 device and the supporting small signal components. connect this ground island to the main ground plane at a single point as close to the adm1278-1 gnd pin as possible. see the adm1278 evaluation board ( eval-adm1278ebz ) as an example. 23 pgnd pgnd power ground. this pin is the ground return path for the strong gate pull-down current. it is also the ground return for the external tran sistor used for temperature measurements. 24 gate gate gate output. this pin is the high-side gate drive of an external n-channel fet. this pin is driven by the fet drive controller, which uses a charge pump to provide a pull-up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held low when the supply is below the undervoltage lockout threshold (uvlo). 25 temp temp temperature input. an external npn device can be placed close to the mosfets and connected back to the temp pin to report temperature. the voltage at the temp pin is measured by the internal adc.
data sheet adm1278 mnemonic pin no. adm1278 - 1 adm1278 - 3 description 26 mo? mo? negative power monitor input. a sense resistor between the mo+ pin and the mo? pin sets the sense voltage that is used by the adc internally to measure load current. extra filtering can be added between the mo+ and mo? pins if required. 27 hs? hs? neg ative current sense input. a sense resistor between the hs+ pin and the hs? pin sets the analog current limit. the hot swap operation of the adm1278 - 1 controls the external fet gate to maintain the sense voltage (v hs+ ? v hs? ). 28 hs+ hs+ positive current sense input. this pin connects to the main supply input. a sense resistor between the hs+ pin and the hs? pin sets the analog current limit. the hot swap operation of the adm1278 -1 controls the external fet gate to maintain the sense voltage (v hs+ ? v hs? ). this pin is also used to measure the supply input voltage using the adc. 29 mo+ mo+ positive power monitor in put. a sense resistor between the mo+ pin and the mo? pin sets the sense voltage that is used by the adc internally to measure load current. extra filtering can be added between the mo+ and mo? pins if required. 30 vcc vcc positive supply input. a uvlo ci rcuit resets the device when a low supply voltage is detected. gate is held low when the supply is below uvlo. during normal operation, it is recommended that this pin be greater than or equal to hs+ and mo+ to ensure that specifications are adhered to. no sequencing is required. 31 uv uv undervoltage input. an external resistor divider is configured from the input supply to this pin to allow an internal comparator to detect whether the supply is below the uv limit. 32 ov ov overvoltage input. an external resistor divider is configured from the input supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. ep ep exposed pad. solder the exposed pad to the board to improve thermal dissipation. the exposed pad can be connected to ground. rev. a | page 13 of 61
adm1278 data sheet notes 1. solder the exposed pad to the board to improve thermal dissipation. the exposed pad can be connected to ground. 1 pset 2 vca p 3 iset 4 is t art 5 timer 6 f au l t 7 adr1 8 adr2 24 ga te 23 pgnd 22 gnd 21 pwgin 20 vout 19 csout 18 pwrgd 17 ret r y 9 spi_ss 10 mclk 1 1 md a t 12 enable 13 gpo1/alert1/conv 14 gpo2/alert2 15 sd a 16 sc l 32 ov 31 uv 30 vcc 29 mo+ 28 hs+ 27 hs? 26 mo? 25 tem p adm1278-2 t op view (not to scale) 12198-105 figure 6. adm1278 - 2 pin configuration table 9 . adm1278 - 2 pin function descriptions pin no. mnemonic description 1 pset power limit. this pin allows the constant power limit to be programmed. the current limit is dynamically adjusted to ensure that the maximum power dissipation in the fet never exceeds this limit during any operating condition. the power limit can be adjust ed to a user defined value using a resistor divider from vcap. an external reference can also be used. the fet power is limited to (v pset 8)/(50 r sense ). 2 vcap internal regulated supply. place a capacitor with a value of 1 f or greater on this pin to maintain accuracy. this pin can be used as a reference to program the iset pin voltage. 3 iset current limit. this pin allows the current - limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. to achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from vcap. an external reference can also be used. 4 istart start - up current limit. this pin allows a separate start - up current limit to be set for dv/dt power - up mo de. when powering up in dv/dt mode, the current charging the capacitor is constant and is typically much smaller than the normal load current. the istart pin sets the start - up current limit in a similar manner as iset is used to set the normal current limi t. the start - up current limit is only active while pwrgd is low. the start - up current limit can also be set over pmbus with the strt_up_iout_lim register. start - up current limit = v iset (strt_up_iout_lim/16). the lowest of all the active current limits a lways takes priority. 5 timer timer. an external capacitor, c timer , sets an initial timing cycle delay and a fault delay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 6 fau lt fault. this pin asserts low and latches after a fault has occurred. the faults that can trigger this pin include an overcurrent fault resulting in the timer pin voltage exceeding the upper threshold, an overtemperature fault, and an fet health fault. this is an open - drain output pin. 7, 8 adr1, adr2 pmbus address. these pins can be tied to gnd, tied to vcap, left floating, or tied low through a resistor for a total of 16 unique pmbus device addresses ( see the device addressing section ). 9 spi_ss slave select. when pulled low, this pin begins to transfer data on the mdat line. 10 mclk master clock. the mclk signal o utput s data on the mdat line. t his pin is clocked by an external device. 11 mdat master data output. open - drain output. requires an external pull - up resistor . the mdat pin is an output only pin and can be used to stream data from the adc. there is a fixed format for the current, voltage, and temperature data, and no header information is required. this pin is high impeda nce when not transmitting data. 12 enable enable. this pin is an active high digital input pin. this input must be high to allow the adm1278 - 2 hot swap controller to begin a power - up sequence. if this pin is held low, the adm1278- 2 is prevented from initiating a hot swap attempt. rev. a | page 1 4 of 61
data sheet adm1278 rev. a | page 15 of 61 pin no. mnemonic description 13 gpo1/ alert1 /conv general-purpose digital output (gpo1). alert (alert1 ). this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. conversion (conv). this pin can be used as an input signal to control when a power monitor adc sampling cycle begins. the gpo1/alert1 /conv pin defaults to an alert output at power-up. this is an open-drain output pin. 14 gpo2/alert2 general-purpose digital output (gpo2). alert (alert2 ). this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. the gpo2/alert2 pin defaults to an alert output at po wer-up. this is an open-drain output pin. 15 sda serial data input/output. open-dra in input/output. requires an external pull-up resistor. if the i 2 c pins, sda and scl, are not used, tie them to gnd or via a resistor pull-up to vcap or another supply. this avoids any glitches on the i 2 c pins being interpreted as i 2 c transactions. 16 scl serial clock. open-drain input. requires an external pull-up resistor. if the i 2 c pins, sda and scl, are not used, tie them to gnd or via a resistor pull-up to vc ap or another supply. this avoids any glitches on the i 2 c pins being interpreted as i 2 c transactions. 17 retry retry. the retry pin has an internal pull-up resistor; therefore, it can be left floating to enable the default latch off mode after an overcurrent fault. this pin can be pulled low to enable a 10 second autoretry following an overcurrent fault. 18 pwrgd power-good signal. this pin indicates that the supply is within tolerance (pwgi n input), no faults have been detected, and the adm1278-2 hot swap is enabled with the gate fully enhanced. this is an open drain output pin. 19 csout current sense output. the v sense_hs voltage is amplified to give an output voltage corresponding to the load current. 20 vout output voltage. vout is an input pin and is used to read back the output voltage using the internal adc. insert a 1 k resistor in series between the source of a fet and the vout pin. this pin is also used along with hs? to calculate th e drain to source voltage (v ds ) of the fet for constant power foldback operation. 21 pwgin power-good input. this pin sets the power-good input threshold. the user can set an accurate power- good threshold with a resistor divider from the sour ce of the fet (vout). the pwrgd output signal is not asserted high until the output voltage is above the threshold set by this pin. 22 gnd ground. this pin is the ground connection for all of th e sensitive analog nodes. take care to isolate this ground connection from the main high current path and any large transients. a good technique for this is to create a ground island around the adm1278-2 device and the supporting small signal components. connect this ground island to the main ground plane at a single point as close to the adm1278-2 gnd pin as possible. see the adm1278 evaluation board ( eval-adm1278ebz ) as an example. 23 pgnd power ground. this is the ground return path for th e strong gate pull-down current. it is also the ground return for the external transistor used for temperature measurements. 24 gate gate output. this pin is the high-side gate drive of an external n-channel fet. this pin is driven by the fet drive controller, which uses a charge pump to provide a pull-up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held low when the supply is below the uvlo threshold. 25 temp temperature input. an external npn device can be placed close to the mosfets and connected back to the temp pin to report temperature. the voltage at the temp pin is measured by the internal adc. 26 mo? negative power monitor input. a sense resistor between the mo+ pin and the mo? pin sets the sense voltage that is used by the adc internally to measure load current. extra filtering can be added between the mo+ and mo? pins if required. 27 hs? negative current sense input. a se nse resistor between the hs+ pin and the hs? pin sets the analog current limit. the hot swap operation of the adm1278-2 controls the external fet gate to maintain the sense voltage (v hs+ ? v hs? ). 28 hs+ positive current sense input. this pin connects to the main supply input. a se nse resistor between the hs+ pin and the hs? pin sets the analog current limit. the hot swap operation of the adm1278-2 controls the external fet gate to maintain the sense voltage (v hs+ ? v hs? ). this pin is also used to measure the supply input voltage using the adc. 29 mo+ positive power monitor input. a sense resistor between the mo+ pin and the mo? pin sets the sense voltage that is used by the adc internally to measure load current. extra filtering can be added between the mo+ and mo? pins if required.
adm1278 data sheet pin no. mnemonic description 30 vcc positive supply input. a uvlo circuit resets the device when a low supply voltage is detected. gate is held low when the supply is below uvlo. during normal operation, it is recommended that this pin be greater than or equal to hs+ and mo+ to ensure that specifications are adhered to. no sequencing is required. 31 uv undervoltage input. an external resistor divider is configured from the input supply to this pin to allow an internal comparator to detect whether the supply is below the uv limit. 32 ov overvoltage input. an external resistor divider is configured fro m the input supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. ep exposed pad. solder the exposed pad to the board to improve thermal dissipation. the exposed pad can be connected to ground. rev. a | page 16 of 61
data sheet adm1278 typical performance characte ristics 0 1 2 3 4 5 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i cc (ma) temper a ture (c) 12198-208 figure 7 . supply current (i cc ) vs. temperature 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 v cc (v) i cc (ma) 12198-209 figure 8 . supply current (i cc ) vs. v cc 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i ga tedn_slow (ma) temper a ture (c) 12198-210 figure 9 . gate pull - down current (i gatedn_slow ) vs. temperature 0 80 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i ga tedn_reg (a) temper a ture (c) 12198-207 10 20 30 40 50 60 70 figure 10 . gate pull - down current (i gatedn_reg ) vs. temperature ?30 ?25 ?20 ?15 ?10 ?5 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i g a teup (a) temper a ture (c) 12198-2 1 1 figure 11 . gate pull - up current (i gateup ) vs. temperature 0 5 10 15 20 25 30 35 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v ga te (v) temper a ture (c) v cc = 8v v cc = 5v v cc = 20v 12198-212 figure 12 . v gate (5 a l oad ) vs. temperature rev. a | page 17 of 61
adm1278 data sheet 0 2 4 6 8 10 12 14 16 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 ga te drive (v) temper a ture (c) v cc = 8v v cc = 5v v cc = 20v 12198-213 figure 13 . gate drive (5 a load ) vs. temperature 0 5 10 15 20 25 30 35 0 5 10 15 v g a te (v) v cc (v) 12198-214 figure 14 . v gate (5 a load ) vs. v cc 0 2 4 6 8 10 12 14 16 0 5 10 15 20 ga te drive (v) v cc (v) 12198-215 figure 15 . gate drive vs. v cc 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 0 5 10 15 20 25 i g a tedn_slow (ma) v cc (v) 12198-216 figure 16 . i gatedn_slow vs. v cc ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i timeruppor (a) temper a ture (c) 12198-217 figure 17 . timer pull - up current por (i timeruppor ) vs. temperature ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i timerupf l t (a) temper a ture (c) 12198-218 figure 18 . timer pull - up current oc fault (i timerupflt ) vs. temperature rev. a | page 18 of 61
data sheet adm1278 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0 5 10 15 20 i timeruppor (a) v cc (v) 12198-219 figure 19 . timer pull - up current por (i timeruppor ) vs. v cc ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 5 10 15 20 i timerupf l t (a) v cc (v) 12198-223 figure 20 . timer pull - up current oc fault (i timerupflt ) vs. v cc temper a ture (c) 0 1 2 3 4 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i timerdnrt (a) 12198-220 figure 21 . timer pull - down current retry (i timerdnrt ) vs. temperature temper a ture (c) 0 10 20 30 40 50 60 70 80 90 100 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 i timerdnhold (a) 12198-221 figure 22 . timer pull - down current hold (i tmerdnhold ) vs. temperature temper a ture (c) 0 100 200 300 400 500 600 700 800 900 1000 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v timerl (mv) 12198-224 figure 23 . timer low threshold (v timerl ) vs. temperature temper a ture (c) 0 100 200 300 400 500 600 700 800 900 1000 1 100 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v timerh (mv) 12198-226 figure 24 . timer high threshold (v timerh ) vs. temperature rev. a | page 19 of 61
adm1278 data sheet temper a ture (c) 900 950 1000 1050 1 100 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 uv threshold (mv) uv threshold low (mv) uv threshold high (mv) 12198-227 figure 25 . uv threshold vs. temperature ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 temper a ture (c) 0 10 20 30 40 50 60 70 80 90 100 uv hysteresis (mv) 12198-228 figure 26 . uv hysteresis vs. temperature temper a ture (c) temper a ture (c) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 900 950 1000 1050 1 100 ov thresh old (mv) uv threshold low (mv) uv threshold high (mv) 12198-229 figure 27 . ov threshold vs. temperature temper a ture (c) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 90 100 ov hysteresis (mv) 12198-230 figure 28 . ov hysteresis vs. temperature temper a ture (c) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 900 950 1000 1050 1 100 pwgin threshold (mv) pwgin threshold low (mv) pwgin threshold high (mv) 12198-231 figure 29 . pwgin threshold vs. temperature temper a ture (c) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 90 100 pwgin hysteresis (mv) 12198-232 figure 30 . pgin hysteresis vs. temperature rev. a | page 20 of 61
data sheet adm1278 0 2 4 6 8 10 12 14 16 0 10 20 30 40 50 60 csout vo lt age (v) v sense (mv) 12198-233 figure 31 . csout voltage vs. v sense 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 csout error (%) v sense (mv) 12198-234 figure 32 . csout error vs. v sense 0 50 100 90 80 code 70 60 40 30 20 10 150 140 130 120 1 10 2834 2836 2838 2840 2842 2844 2846 2848 2850 2852 2854 2856 2858 2860 2862 2864 128 16 no a vg 12198-236 occurrence figure 33 . adc code histogram (v sense = 10 mv, 200 measurements) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 measurement error (c) externa l transis t or temper a ture (c) 12198-235 figure 34 . measurement error vs. external transistor temperature ch2 5.00v m5.00s ch2 19.8v 2 12198-032 figure 35 . vgate response to severe overcurrent event (gate fast pull - down) 0 0.2 0.4 0.6 0.8 0 1 2 3 4 5 6 v ol (v) i ol (ma) v cc = 12v v cc = 4.5v 12198-033 figure 36 . pwgd pin, v ol vs. i ol rev. a | page 21 of 61
adm1278 data sheet 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 v sense (mv) is t art code (strt_up_iout_lim) v cb v sensec l 12198-034 figure 37 . v sense vs. istart code (strt_up_iout_lim) 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v sense (mv) is t art vo lt age (v) v cb v sensec l 12198-035 figure 38 . v sense vs. istart voltage 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v sensecl (mv) v pset v ds = 4v v ds = 8v v ds = 20v 12198-036 figure 39 . v sensecl vs. v pset ?50 0 50 100 150 200 250 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i mo+ / i mo? (na) v mo+ = v mo? (v) 12198-130 figure 40 . i mo+ /i mo vs. v mo+ /v mo with v cc = 20 v ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i mo+ / i mo? (na) v mo+ = v mo? (v) 12198-131 figure 41 . i mo+ /i mo vs. v mo+ / v mo with v cc = v mo+ = v mo ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 10 20 30 40 50 60 70 80 90 100 i mo+ (na) v sense (mv) 12198-132 figure 42 . i mo+ vs. v sense with v cc = v mo+ = 20 v rev. a | page 22 of 61
data sheet adm1278 i mo? (na) ?10 0 10 20 30 40 50 60 70 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 v sense (mv) 12198-133 figure 43 . i mo? vs. v sense with v cc = v mo+ = 20 v 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 0 5 0 10 0 15 0 i hs+ /i hs? ( a ) v h s + (v) 12198 - 134 figure 44 . i hs+ /i hs vs. v hs+ rev. a | page 23 of 61
adm1278 data sheet theory of operation when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. these transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. t he adm1278 is designed to control the powering on and off of a system in a controlled manner, allowing a board to be removed from, o r inserted into, a live backplane by protecting it from excess currents. the adm1278 can reside on the backplane or on the removable board. powering the adm1278 a supply voltage from 4.5 v to 20 v is required to power the adm1278 via the vcc pin. the vcc pin provides the majority of the bias current for the device; the remainder of the current needed to control the gate drive and to best regulate the v gs voltage is supplied by the hs+ pin. to ensure correct operation of the adm1278 , the voltage on the vcc pin must be greater than or equal to t he voltage on the hs+ and mo+ pins. no sequencing of the vcc and hs+ rails is necessary. the hs+ pin can be as low as 2 v for normal operation, provided that a voltage of at least 4.5 v is connected to th e vcc pin. in most applications, both the vcc and hs + pins are connected to the same voltage rail, but they are connected via separate traces to prevent accuracy loss in the sense voltage measurement (see figure 45). 4.5v to 20v r sense q 1 hs? gnd gate vcc hs+ adm1278 12198-005 figure 45 . powering the adm1278 to protect the adm1278 from unnecessary resets due to transient supply glitches, an external resistor and capacitor can be added, as shown in figure 46 . ch oose the values of these components such that a time constant is p rovided that can filter any expected glitches. however, use a resistor that is small enough to keep voltage drops caused by quiescent current to a minimum. unless a resistor is used to limit the inrush current, do not place a supply decoupling c apacitor on the rail before the fet. 4.5v to 20v r sense q 1 hs? gnd gate vcc 330nf hs+ 22? adm1278 12198-006 figure 46 . transient glitch protection using an rc network hot swap current sen se inputs the load current is monitored by measuring the voltage drop across an external sense resistor, r sense (see figure 47 ). an internal current sense amplifier provides a gain of 50 to the voltage drop detected across r sense . the result is compared to an internal reference and used by the hot swap control logic to detect when an overcurrent condition occurs. r sense q 1 hs? gnd gate vcc hs+ adm1278 over- current reference 50 + + ? ? 12198-007 figure 47 . hot swap current sense amplifier the hs inputs can be con nected to multiple parallel sense resistors, which can affect the voltage drop detected by the adm1278 . the current flowing through the sense resistors creates an offset, resulting in reduced ac curacy. to achieve better accuracy, averaging resistors can be used to sum the current from the nodes of each sense resistor, as shown in figure 48 . a ty pical value for the averaging resistors is 10 . the input current to each sense pin is matched to within 5 a. this ensures that the same offset is observed by both sense inputs. rev. a | page 24 of 61
data sheet adm1278 q 1 hs? gnd gate vcc hs+ bias current 2v to 20v 12198-008 figure 48 . connection of multiple sense resistors to the hs pins power monitor curren t sense inputs the internal adc uses separate current sense input pins for measuring the load current from those used by the hot swap circuitry. this allows additional filtering on the power monitor pins withou t affecting the response time of the ho t swap to an overcurrent event. the same external sense resistor, r sense , is used for hot swap control and adc measurements. if additional external filtering is not required, the hs and mo pins can be tied together, close to the device under test, as shown in figure 49. q 1 hs? gnd gate vcc hs+ mo+ mo? r sense 12198-009 figure 49 . power monitor no external filtering if additional antial iasing filtering is required, filtering components can be added , as shown in figure 50, without affecting the hot swap performance. r se n s e mo+ mo? hs+ adm1278 h s? adc hs contro l 12198-010 + ? + ? figure 50 . power monitor current sense filtering current - limit reference the current - limit reference voltage determines the load current level to which the adm1278 limits the current during an overcurrent event. this reference voltage is compared to the amplified current sense voltage to determine whether the limit is reached. an internal current - limit reference selector block continuously compares the iset and pset voltages to determine which voltage reference is the lowest at any given time; the lowest voltage is used as the current - limit reference. the istart pin is also monitored while pwrgd is inac tive. this ensures that the pro grammed current limit, iset, is us ed in normal operation, and that the start - up current limit and foldback features reduce the current limit when required during startup and/or fault conditions. r sense q 1 hs? gnd gate vcc iset pset istart hs+ adm1278 over- current 50 12198-0 1 1 figure 51 . current - limit reference selection the foldback and start - up current - limit voltage inputs to the internal comparator are clamped to minimum levels of 100 mv (that is, v sensecl = 2 mv) to prevent zero current flow caused by the current limit being too low. figure 52 provides an ex ample of how the istart, pset, and iset voltages interact during startup as the adm1278 is enhancing the fet and charging the output load capacitance. istart pset iset 1v 0 .1v v vout current-limit reference pwrgd 12198-012 figure 52 . interaction of istart, pset, and iset current limits rev. a | page 25 of 61
adm1278 data sheet rev. a | page 26 of 61 setting the current limit (iset) the maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. however, as currents become larger, the sense resistor requirements become smaller, and resolution can be difficult to achieve when selecting the appropriate sense resistor. the adm1278 provides an adjustable current sense voltage limit to manage this issue. the device allows the user to program the required current sense voltage limit from 5 mv to 25 mv. the default value of 20 mv is achieved by connecting the iset pin directly to the vcap pin. this connection configures the device to use an internal 1 v reference, which equates to 20 mv at the sense inputs (see figure 53). adm1278 vcap iset c1 gnd 12198-013 figure 53. fixed 20 mv current sense limit to program the sense voltage from 5 mv to 25 mv, a resistor divider is used to set a reference voltage on the iset pin (see figure 54). adm1278 gnd vcap iset c1 r1 r2 12198-014 figure 54. adjustable 5 mv to 25 mv current sense limit the vcap pin has a 2.7 v internal generated voltage that can be used to set a voltage at the iset pin. assuming that v iset equals the voltage on the iset pin, size the resistor divider to set the iset voltage as follows: v iset = v sensecl 50 where v sensecl is the current sense voltage limit. the vcap rail can also be used as the pull-up supply for the resistor divider on the pset and istart pins and for setting the i 2 c address. do not use the vcap pin for any other purpose. to guarantee accuracy specifications, do not load the vcap pin by more than 100 a. setting a linear output voltage ramp at power-up the adm1278 standard method of power-up in a server application is to configure a single linear voltage ramp on the output, which allows a constant inrush current into the load capacitance. this method has the advantage of setting very low inrush currents where required by a combination of large output capacitance and fet soa limitations. the object of such a design is to allow a linear monotonic power-up event without the restrictions of the system fault timer. to achieve this, a power-up ramp is set such that the inrush is low enough not to reach the active circuit breaker current limit. this allows the power-up to continue without the timer running. when using this method, ensure that the power in the mosfet during this event meets the soa requirements. an extra component, c gate , is required on the gate pin as shown in figure 55. 4.5v to 20v r sense q 1 hs? gnd gate vcc hs+ adm1278 pgnd c gate 12198-015 figure 55. dv/dt power-up configuration to ensure that the inrush current does not approach or exceed the active current-limit level, the output voltage ramp can be set by selecting the appropriate value for c gd as follows: c gate = (i gateup / i inrush ) c load where i gateup is the gate pull-up current specified. add margin and tolerance as necessary to ensure a robust design. subtract any parasitic c gd of the mosfets from the total to determine the additional external capacitance required. next, the power-up ramp time can be approximated by t ramp = ( v in c load )/ i inrush = ( v in c gate )/ i gateup check the soa of the mosfet for conditions and the duration of this power-up ramp. timer regulation period can be minimized to provide a simple fault filtering solution. the diagram in figure 56 shows a typical hot swap power-up with a gate capacitor configured for a linear output voltage ramp.
data sheet adm1278 0v 12v 0v 1v 12v 24v 0a ~3a typ 0v 12v 16v 0v vout gate por time set by timer capacitor (min 27ms) output voltage ramp set by gate capacitor vcc/ enable timer gate/ vout i out pwrgd (pull-up to vcc) current limit cl = istart (for example, 10a) 12198- 1 16 cl = iset (for example, 60a) figure 56 . linear voltage ramp power - up start - up current limit when powering up in dv/dt mode, the inrush current is typically configured to be in the order of <5 a. the other active current limits (pset and iset) may be much higher than this. the start - up current limit is intended as an extra level of protection during this initial power - up stage. it helps catch a re sistive type fault that causes the inrush to be highe r than expected. the start - up current limit is only active during power - up. it is enabled while pwrgd is deasserted and is d isabled when pwrgd is asserted. the start - up current limit can be programmed vi a the istart pin or via the pmbus register, strt_up_iout_lim (register 0xf6). if both are configured, the lowest current limit is selected as the active current limit. the clamp level in both cases is a 2 mv v sense current limit. when configuring with the i start pin, the current limit is sense istart r v cl startup = 50 _ more importantly, the circuit breaker level can be calculated using the following equation: sense istart r v cb startup ? ? ? ? ? ? ? = mv 88 . 0 50 _ to prevent the start - up current limit from being triggered during a normal dv/dt powe r - up, set the circuit breaker level above the maximum expected inrush current. the istart pin can be tied to vcap to disable the start - up current limit. the start - up current limit pmbus register is set to the maximum by default; therefore, it is effectivel y disabled by default. if configuring the start - up current limit with the pmbus register, the start - up current limit is set as a fraction of the iset current limit. there are four register bits so that the start - up current limit can be set from 1/16 th to 1 6/16 th of the normal current limit. the effective ista rt voltage can be calculated as ( ) ? ? ? ? ? ? + = 16 1 _ _ _ lim iout up strt v v iset istart rev. a | page 27 of 61
adm1278 data sheet the start - up circuit breaker and current limits can then be calculated from this effective istart voltage. constant power foldb ack foldback is a me thod that actively reduces the current limit as the voltage drop across the fet increases. it keeps the power across the fet below the programmed value during power - up, overcurrent, or short - circuit events. this allows a smaller fet to be used, resulting i n board size savings and cost savings. the foldback method used is a constant power foldback scheme, meaning power in the fet is held constant, regardless of the v ds of the fet. this simplifies the task of ensuring that the fet is always operating within t he soa limits. the adm1278 detects the v ds voltage drop across the fet by sensing the hs+ and vout pins. the foldback current limit dynamically changes as the v ds voltage changes to maintain a constant power level in the mosfet. for example, a s v out drops, the current - limit reference follows v pset after it becomes the lowest voltage input to the current - limit reference selector block. this results in a reduction of the current limit and, therefore , the regulated load current. to prevent compl ete current flow restriction, a clamp becomes active when the current - limit reference reaches 100 mv. the current limit cannot drop below this level. the maximum fet power level is configured with a resistor divider on the pset pin ( ) ( ) sense pset r v limit power fet = 50 8 therefore, after determining the desired fet power limit and r sense values, the required pset voltage can be calculated. set t his voltage with a resistor divider from the vcap pi n. timer the timer pin handles several timing functions with an external capacitor, c timer . the two comparator thresholds are v timerl (0.2 v) and v timerh (1 v). there are four timing current sources: a 3 a pull - up, a 60 a pull - up, a 2 a pull - down, and a 100 a pull - down. these current and voltage levels, together with the value of c timer chosen by the user, determine the initial timing cycle time and the fault regulation time. the timer pin capacitor value is determine d using the following equation: c tim er = ( t on 60 a)/ v timerh where t on is the time that the fet is allowed to spend in regu l ation at the set current limit. the choice of fet is based on matching this time with the soa requirements of the fet. foldback can be used to simplify the selection. when vcc is connected to the backplane supply, the internal supply of the adm1278 must be charged up. in a very short time, the internal supply is fully charged up and, because the uvlo voltage is exceeded at vcc, the device emerges from reset. during this first short reset period, the gate and timer pins are both held low. the adm1278 then goes through an initial timing cycle. the ti mer pin is pulled high with 3 a . when the timer pin reaches the v timerh threshold (1.0 v), the first portion of the initial timing cycle is complete. the initial timing cycle is a minimum of approximately 27 ms to allow fet health checks to be completed. if the initial timer cycle is set shorter than 27 ms by the timer capacitor, the timer pin continues to be pulled up to the vcap voltage level until the 27 ms has expired. the 100 a current source then pulls down the timer pin until it reaches v timerl (0. 2 v). the initial timing cycle duration is related to c timer by the following equation: a 100 ) ( a 3 timer timerl timerh timer timerh initial c v v c v t ? + = t initial 27 ms, regardless of c timer value. for example, a 100 nf capacitor results in an initial insertion delay of approximately 34 ms. if the uv and ov inputs indicate that the supply is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot swap operation. when the voltage across the sense resistor reaches the circuit breaker trip voltage, v cb , the 60 a timer pull - up current is activated, and the gate begins to regulate the current at the current limit. this initiates a ramp - up on the timer pin. if the sense voltage falls below this circuit breaker trip voltage before the time r pin reaches v timerh , the 60 a pull - up is disabled and the 2 a pull - down is enabled. the circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. there is a small circuit breaker offset, v cbos , which means that the timer pin actually starts ramping a short time before the current reaches the defined current limit. however, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 a pull - up current remains acti ve and the fet remains in regulation. this allows the timer pin to reach v timerh and to initiate the gate shutdown. on the adm1278 , th e fault pin is pulled low immediately and pwrgd is deasserted. in latch - off mode, the timer pin is switched to the 2 a pull - down current when it reaches the v timerh threshold. while the timer pin is being pulled down, the hot swap controller remains off and cannot be turned back on. when the volt age on the timer pin goes below the v timerl threshold, the hot swap controller can be reenabled by toggling the uv pin or by using the pmbus operation command to toggle the on bit from on to off and then on again. rev. a | page 28 of 61
data sheet adm1278 rev. a | page 29 of 61 hot swap retry the retry pin is used to configure latch-off or autoretry mode. the retry pin has an internal pull-up current; therefore, it can be left floating to enable latch-off mode after an overcurrent fault. the retry pin can be pulled low to enable a 10 second autoretry following an overcurrent fault. fet gate drive clamps the charge pump used on the gate pin is capable of driving the pin to v cc + (2 v cc ), but it is clamped to less than 14 v above the hs pins and less than 31 v. these clamps ensure that the maximum v gs rating of the fet is not exceeded. fast response to severe overcurrent the adm1278 features a separate high bandwidth current sense amplifier that detects a severe overcurrent that is indicative of a short-circuit condition. a fast response time allows the adm1278 to handle events of this type that may otherwise cause catastrophic damage if not detected and acted on very quickly. the fast response circuit ensures that the adm1278 can detect an overcurrent event at approximately 125% to 225% of the normal current limit (iset) and can respond to and control the current within 1 s, in most cases. there are four severe overcurrent threshold options and two severe overcurrent glitch filter options selectable via the pmbus registers. undervoltage and overvoltage the adm1278 monitors the supply voltage for undervoltage (uv) and overvoltage (ov) conditions. the uv and ov pins are connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 1 v voltage reference. figure 57 illustrates the voltage monitoring input connections. an external resistor network divides the supply voltage for moni- toring. an undervoltage event is detected when the voltage connected to the uv pin falls below 1 v, and the gate is shut down using the 10 ma pull-down device. similarly, when an overvoltage event occurs and the voltage on the ov pin exceeds 1 v, the gate is shut down using the 10 ma pull-down device. there is a fixed 60 mv hysteresis on the uv and ov pin thresholds. gate hs+ adm1278 gnd hs? gate drive r sense q1 v in 1v 1v i out uv ov vcc 50 +? ? + + ? 12198-016 figure 57. undervoltage and overvoltage supply monitoring power good the power-good (pwrgd) output can be used to indicate whether the output voltage is above a user defined threshold and can, therefore, be considered good. a resistor divider on the pwgin pin sets an accurate power-good threshold on the output voltage. the pwrgd pin is an open-drain output that pulls low when the voltage at the pwgin pin is lower than 1.0 v (power bad). when the voltage at the pwgin pin is above this threshold plus a fixed hysteresis of 60 mv, output power is considered to be good. however, pwrgd asserts only when the following conditions are met: ? pwgin is above the rising threshold voltage. ? hot swap is enabled, that is, the enable pin is high ( enable pin is low), and uv and ov are within range. ? there is no active fault condition, that is, the fault pin has been cleared following any fault condition. ? the mosfet is fully enhanced (gate voltage > vmosfet_drain + 4 v). after all of these conditions are met, the open-drain pull-down current is disabled, allowing pwrgd to be pulled high. pwrgd is guaranteed to be in a valid state for vcc 1 v. if the gate voltage drops below v mosfet_drain + 4 v (that is, no longer meets mosfet fully enhanced condition), pwrgd still remains asserted for 100 ms. if the condition persists for longer than 100 ms, pwrgd is deasserted and an fet health fault is signaled. if any of the other conditions for pwrgd are no longer met, pwrgd is deasserted immediately. fault pin the fault pin asserts when one of the following faults causes the hot swap to shut down: ? fet health fault ? overcurrent fault ? overtemperature fault the fault pin is latched, and it can only be cleared by a rising edge on the enable pin (falling edge on the enable pin), a pmbus operation on command from the off state, or a power_cycle command, assuming no faults are still active. the fault registers are not cleared by the enable/ enable pin or the power_cycle command; they can only be cleared by a pmbus operation off to on command or a clear_faults command.
adm1278 data sheet adm1278 fet hea l th montior over current f au l t over temper a ture f au l t gate temp fault r sense hs+ hs? enable 12198-017 figure 58 . fault pin operation enable/ enable input the adm1278 provides a dedicated enable / enable di gital input pin. the adm1278 - 1 and adm1278 - 2 have an active high enable pin whereas the adm12 78- 3 has an active low enable p in. the enabl e / enable p in allows the adm1278 to remain off by using a hardware signal, even when the voltage on the uv pin is g reater than 1.0 v and the voltage on the ov pin is less than 1.0 v. although the uv pin can be used to provide a digital enable signal, using the enabl e / enable pin for this purpose means that the ability to monitor for undervoltage condit ions is not lost. in addition to the conditions for the uv and ov pins, the adm1278 enable / enable i nput pin must be asserted for the devic e to begin a power - up sequence. current sense output (csout) the adm1278 provides a csout pin voltage output that is proportional to the v sense_hs voltage. csout = v sense_hs 350 the csout voltage is an analog representation of the main system current flowing through r sense . a resistor divider can be added to csout to clamp the voltage output to any downstream devices, provided the maximum load conditions described in table 2 are not exceeded. the response time of the csout pin to a change in v sense voltage is very fast; therefore, it can be used when fast response time is required, for example, power throttling. the csout response time to a 10 mv step in v sense voltage is typically 10 s. remote temperature s ensing the adm1278 provides the capability to measure temperature at a remote location with a single discr ete npn or pnp transistor. the temperature measurements can be read back over the pmbus interface. warning and fault thresholds can also be set on the temperature measurement. exceeding a fault threshold causes the controller to turn off the pass mosfet, d eassert the pwrgd pin, and assert the fault p in. the external transistor is typically placed close to the main pass mosfets to provide an additional level of protection. the controller can then monitor and respond to an elevated mosfet operating temperature. it is not possible to measure temperature at more than one location on the board. place the transistor close to the mosfet for best accuracy. if the transistor is placed on the opposite side of the pcb, use multiple vias to ensure th e optimum transfer of heat fro m the mosfet to the transistor. temperature measurement method a simple method of measuring temperature is to exploit the negative temperature coefficient of a diode by measuring the base - emitter voltage (v be ) of a transistor operated at constant current. however, this technique requires calibration to null the effect of the absolute value of v be , which varies from device to device. the technique used in the adm1278 is to measure the change in v be when the device is operated at three different currents. the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. the temperature sensor takes control of the adc for 64 s (typical) every 6 ms. it takes 12 ms to obtain a new temperature measurement from the adc. remote sensing diode the adm1278 is designed to work with discrete transistors. the transist or can be either a pnp or npn connected as a diode (base shorted to the collector). if an npn transistor is used, the collector and base are connected to the temp pin and the emitter to pgnd. if a pnp transistor is used, the collector and base are connecte d to pgnd and the emitter to temp. the best accuracy is obtained by choosing devices according to the following criteria: ? base - emitter voltage greater than 0.25 v at 6 a, at the highest operating temperature. ? base - emitter voltage less than 0.95 v at 100 a, at the lowest operating temperature. ? base resistance less than 100 ?. ? small variation in h fe (50 to 150) that indicates tight control of v be characteristics. transistors, such as the 2n3904, 2n3906, or equivalent in sot - 23 packages are suitable devices to use. noise filtering for temperature sensors operating in noisy environments, the industry standard practice has been to place a capacitor across the temperature pins to mitigate the effects of noise. however, large capacitances affect the accuracy of t he temperature measurement, leading to a recommended maximum capacitor value of 1000 pf. although this capacitor reduces the noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. the adm1278 has a major advantage over other devices for eliminating the effects of noise on the external sensor. the rev. a | page 30 of 61
data sheet adm1278 rev. a | page 31 of 61 series resistance cancellation feature allows a filter to be con- structed between the external temperature sensor and the device. the effect of any filter resistance seen in series with the remote sensor is automatically cancelled from the temperature result. the construction of a filter allows the adm1278 and the remote temperature sensor to operate in noisy environments. figure 59 shows a low-pass r-c-r filter with the following values: r = 100 and c = 1 nf. this filtering reduces both common-mode noise and differential noise. temp 1nf 100 ? remote t emperature sensor pgnd 100 ? 12198-018 figure 59. filter between remote sensor and adm1278 spi interface the serial peripheral interface (spi) allows the user to output a stream of raw data from the adc as soon as new data is available, removing the bandwidth limitations of the pmbus interface for data readback. the pmbus remains as an active data bus and all configuration and register access must still be completed over the pmbus interface. however, the spi interface can be used at the same time to serially output the adc monitoring data. it is a 3-pin serial interface capable of operating at speeds of up to 1 mhz. the spi pins are only available on the adm1278-2 model. if the adm1278-2 model is used but the spi pins are not required, tie the spi input pins ( spi_ss , mclk) to vcap and the spi output pin (mdat) can be left floating or tied to gnd. spi_ss is the slave select pin, and when it is held low, the mclk pin can be used to clock data out on the mdat serial output pin. the spi_ss pin is also used to frame the output data. the spi pins are compatible with spi mode 0 (cpol = cpha = 0), but it is also possible to launch and capture data on the same clock edge for extra timing margin if required. the interface has the following characteristics: ? mdat is driven by the adm1278 (master input, slave output). spi_ss and mclk are driven by the user, for example, a baseboard management controller (bmc). ? no header or id information required. the 80-bit data format is fixed regardless of adc sampling selection (see figure 60). ? the falling edge of spi_ss activates the serial interface, at which point mclk can be used to clock out data on mdat. the time between spi_ss falling edges must be greater than or equal to the maximum adc sampling time to avoid duplicate data. ? select single shot mode to allow the falling edge of spi_ss to trigger adc sampling (adc convert start signal). ? maximum clock speed (mclk) is approximately 1 mhz. ? the output stream can be stopped at any point in the output frame via a rising edge on the spi_ss pin. ? the msb of each sample is output first. ? the output data line is high impedance when not transmitting. for example, if configuring the spi interface to read back adc current samples (16 bits), 15 mclk falling edges are required to clock out all of the bits after the initial falling edge on spi_ss . these bits can be clocked out at 1 mhz; therefore, with an adc sample time of approximately 165 s, the latency between sample and data is 181 s. see figure 3 for spi timing information. note that the mdat output samples are offset by one sample from the adc. v in 16 bits v out 16 bits temperature 16 bits i out 16 bits p in 16 bits 12198-019 figure 60. output data format spi_ss mclk mdat adc sampling i 1 i 2 i 3 i 0 i 1 i 2 12198-020 figure 61. streaming current data only
adm1278 data sheet v out measurement the vout pin measure s the output voltage after the fet. this voltage is used by the device t o determine the v ds of the mosfet for foldback operation. add a 1 k? resistor in series between the source of the fet and the vout pin. this resistor provides some separation between the adm1278 and the fet source during a fault condition; thus, adm1278 operation is not affected. the vout pin on the adm1278 can also be used to provide an alternate voltage for the power monitor to measure. the user can choose to measure the input voltage at the hs+ pin and/or the output voltage at the vout pin. fet health the adm127 8 provides a comprehensive method of detecting a faulty pass mosfet. when a faulty fet is detected, the following occurs: ? pwrgd is deasserted. ? fault is asserted and latched low. ? fet health pmbus status bits are asserted and latched. this detection feature ensures that any downstream dc - to - dc converters are disabled, limiting the power dissipation in any faulty or overheating fets until the user clears the fault, which can be critical to avoid any catastrophic events due to faulty f ets . a gate to source or gate to drain short is a common type of fet failure. this type of failure is detected by the adm1278 at any time during operation. a less common failure is a drain to sourc e short. this normally occurs due to a board manufacturing defect such as a solder short. this type of failure is detected during the initial power - on reset cycle after power - up or after a 10 second autoretry attempt. there is also an option to disable fet health detection via the pmbus. power throttling the adm1278 provides a number of methods for initiating power throttling of a processor. the simplest method is to configure one of the alert pi ns for hs_inlim_enx (alert 1 and alert 2 configuration registers, bit 4). a latched alert is then generated within a few microseconds after the circuit breaker threshold is exceeded (that is, when the timer pin starts ramping). this signal throttle s the pr ocessor in an attempt to reduce the system current level below the circuit breaker threshold before the t imer regulation period expires. the csout pin can be used for the purposes of power throttling as well . the response time of the csout pin to a v sense step of 10 mv is approximately 10 s. the csout pin can then be fed into a comparator (via a resistor divider) to set a programma ble analog threshold for the system current. the output of the comparator can be used to throttle the processor after the confi gured threshold has been exceeded. the advantage of using the csout pin is that the threshold for power throttling can be configured independently of the active hot swap current limit. however, the accuracy of the csout pin has to be taken into account whe n setting the power throttling threshold. the latest intel ? processors have a fast processor hot (fast prochot) input/output pin that can be used for power throttling. asserting this pin initiates a deep throttle of the processor. this is usually used as a last attempt at throttling to avoid a card shutting down when all else has failed. the hs_inlim _ fault alert signal or the csout pin can be used to drive this fast prochot pin to achieve power throttling. power monitor the adm1278 features an integrated adc that accurately meas - ure s the current sense voltage, the input voltage, and optionally, the output voltage and temperature at an external transistor. t he measured input voltage and current being delivered to the load are multiplied together to give a power valu e that can be read back. each power value is also added to an energy accumulator that can be read back to allow an external device to calculate the energy consumption of the load. the adm1278 report s the measured current, input voltage, output voltage, and temperature. the peak_iout, peak_vin, peak_vout, peak_pin, and peak_temperature commands can be used to read the highest readings since the value was last cleared. an averaging function is provided for voltage, current, and power that allows a number of samples to be averaged together by the adm1278 . this function reduces the need for postprocessing of sampled data by the host processor. the number of samples that can be averaged is 2 n , where n is in the range of 0 to 7. the power monitor current sense amplifier is bipolar and measu re s both positive and negative cu rrents. the power monitor amplifier has an input range of 25 m v. the two basic modes of operation for the power monitor are single shot and continuous. in single shot mode, the adc samples the input voltage and current a number of times, depending on the averaging value selected by the user. the adm1278 returns a single value corresponding to the average voltage and current measured. when configured for continuous mode, the power monitor continu ously samples the voltage and current, making the most recent sample available to be read. the single shot mode can be tri ggered in a number of ways. the simplest method is by selecting the single shot mode using the pmon_config command and writing to the convert bit using the pmon_control command. the convert bit can also be written as part of a pmbus group command. using a group command allows multiple devices to be written to as part of the same i 2 c bus transaction, with all devices executing the command when the stop condition appears on the bus. in this way, several devices can be triggered to sample at the same time. rev. a | page 32 of 61
data sheet adm1278 each time current sense and input voltage measurements are taken, a power calculation is performed, multiplying the two measurements tog ether. this can be read from the device using the read_pin comm and, returning the input power. at the same time, the calculated power value is added to a power accumulator register that may increment a rollover counter if the value exceeds the maximum accu mulator value. the power accumulator register also increments a power sample counter. the power accumulator and power sample counter are read using the same read_ein command to ensure that the accumulated value and sample count are from the same point in t ime. the bus host reading the data assigns a time stamp when the data is read. by calculating the time difference between consecutive uses of read_ein and determining the delta in power consumed, it is possible for the host to determine the total energy co nsumed over that period. rev. a | page 33 of 61
adm1278 data sheet rev. a | page 34 of 61 pmbus interface the i 2 c bus is a common, simple serial bus used by many devices to communicate. it defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. smbus is based on i 2 c and aims to provide a more robust and fault tolerant bus. functions such as bus timeout and packet error checking are added to help achieve this robustness, together with more specific definitions of the bus messages used to read and write data to devices on the bus. pmbus is layered on top of smbus and, in turn, on i 2 c. using the smbus defined bus messages, pmbus defines a set of standard commands that can be used to control a device that is part of a power chain. the adm1278 command set is based on the pmbus? power system management protocol specification , part i and part ii, revision 1.2. this version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. however, many of the standard pmbus commands can be mapped directly to the functions of a hot swap controller. part i and part ii of the pmbus standard describe the basic commands and their use in a typical pmbus setup. the following sections describe how the pmbus standard and the adm1278 specific commands are used. device addressing the adm1278 is available in three a grade models: the adm1278-1 , adm1278-2 , and adm1278-3 . there is also an aa grade version of the adm1278-1 with improved power monitoring accuracy and a b grade version with lower power monitoring accuracy. the pmbus device address is seven bits in size. there are no default addresses for any of the models; any device can be programmed to any of 16 possible addresses. two quad level adrx pins map to the 16 possible device addresses. table 10. adrx pin connections adrx state adrx pin connection low connect to gnd resistor 150 k resistor to gnd high-z no connection (floating) high connect to vcap table 11. pmbus address decode (7-bit address) adr2 state adr1 state device address (hex) low low 0x10 low resistor 0x11 low high-z 0x12 low high 0x13 resistor low 0x40 resistor resistor 0x41 resistor high-z 0x42 resistor high 0x43 high-z low 0x44 high-z resistor 0x45 high-z high-z 0x46 high-z high 0x47 high low 0x50 high resistor 0x51 high high-z 0x52 high high 0x53 smbus protocol usage all i 2 c transactions on the adm1278 are performed using smbus defined bus protocols. the following smbus protocols are implemented by the adm1278 : ? send byte ? receive byte ? wr ite byte ? read byte ? wr ite word ? read word ? block read packet error checking the adm1278 pmbus interface supports the use of the packet error checking (pec) byte that is defined in the smbus standard. the pec byte is transmitted by the adm1278 during a read transaction or sent by the bus host to the adm1278 during a write transaction. the adm1278 supports the use of pec with all the smbus protocols that it implements. the use of the pec byte is optional. the bus host can decide whether to use the pec byte with the adm1278 on a message by message basis. there is no need to enable or disable pec in the adm1278 . the pec byte is used by the bus host or the adm1278 to detect errors during a bus transaction, depending on whether the transaction is a read or a write. if the host determines that the pec byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. if the adm1278 determines that the pec byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag.
data sheet adm1278 rev. a | page 35 of 61 within a group command, the host can choose whether to send a pec byte as part of the message to the adm1278 . partial transactions on i 2 c bus if there is a partial transaction on the i 2 c bus (for example, spurious data interpreted as a start command), the adm1278 i 2 c bus is not locked up, thinking it is in the middle of an i 2 c transaction. a new start command is recognized even in the middle of another transaction. smbus message formats figure 62 to figure 70 show all the smbus protocols supported by the adm1278 , along with the pec variant. in these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the adm1278 is driving the bus. figure 62 to figure 70 use the following abbreviations: ? s is the start condition. ? sr is the repeated start condition. ? p is the stop condition. ? r is the read bit. ? w is the write bit. ? a is the acknowledge bit (0). ? a is the acknowledge bit (1). a, the acknowledge bit, is typically active low (logic 0) when the transmitted byte is successfully received by a device. however, when the receiving device is the bus master, the acknowledge bit for the last byte read is a logic 1, indicated by a . sp a aw slave address data byte s p a aw slave address data byte pec a master to slave slave to master 12198-021 figure 62. send byte and send byte with pec sp a ar slave address data byte s p a ar slave address data byte pec master to slave slave to master a 12198-022 figure 63. receive byte and receive byte with pec sa aw slave address command code data byte pa sa aw slave address command code data byte p a pec a master to slave slave to master 12198-023 figure 64. write byte and write byte with pec a slave address r data byte sr a a s a aw slave address command code pa pec sa aw slave address command code slave address p rdata byte sr a master to slave slave to master 12198-024 figure 65. read byte and read byte with pec p sa aw slave address command code data byte low a a sa aw slave address command code data byte low adata byte high data byte high a pa pec master to slave slave to master 12198-025 figure 66. write word and write word with pec
adm1278 data sheet sr a sla ve address a r s a w sla ve address command code a dat a byte low p a a a dat a byte high sr a sla ve address a r s a w sla ve address command code a dat a byte low dat a byte high p pec master t o sl a ve sla ve t o master 12198-026 figure 67 . read word and read word with pec sr a sla ve address a r s a w sla ve address command code a byte count = n a dat a byte 1 p dat a byte n a dat a byte 2 sr a sla ve address a r s a w sla ve address command code a byte count = n a dat a byte 1 a dat a byte n p pec a dat a byte 2 master t o sl a ve sla ve t o master a a 12198-027 figure 68 . block read and block read with pec master t o sl a ve sl a ve t o master a low d at a byte a s a w device 1 address command code 1 a high d at a byte one or more d at a bytes a low d at a byte a sr a w device 2 address command code 2 a high d at a byte one or more d at a bytes a low d at a byte a sr a w device n address command code n a p high d at a byte one or more d at a bytes 12198-028 figure 69 . group command master t o sl a ve sla ve t o master a pec 1 p a low d at a byte a s a w device 1 address command code 1 a high d at a byte one or more d at a bytes a pec 2 a low d at a byte a sr a w device 2 address command code 2 a high d at a byte one or more d at a bytes a pec n a low d at a byte a sr a w device n address command code n a high d at a byte one or more d at a bytes 12198-029 figure 70 . group command with pec rev. a | page 36 of 61
data sheet adm1278 group commands the pmbus standard defines what are known as group commands. group commands are single bus transactions that send commands or data to more than one device at the same time. each device is addressed separately, using its own address; there is no special group command address. a group command transaction can contain only write commands that send data to a device. it is not possible to use a group command to read data from devices. from an i 2 c protocol point of view, a normal write command consists of the following: ? i 2 c start co ndition. ? slave address bits and a write bit (followed by an acknowledge from the slave device). ? one or more data bytes (each of which is followed by an acknowledge from the slave device). ? i 2 c stop condition to end the transaction. a group command differs f rom a nongroup command in that after the data is written to one slave device, a repeated start condition is placed on the bus followed by the address of the next slave device and data. this continues until all of the devices have been written to, at which point the stop condition is placed on the bus by the master device. the format of a group command and a group command with pec is shown in figure 69 and figure 70 , respectively. each device that is written to as part of the group co mmand does not immediately execute the command written. the device must wait until the stop condition appears on the bus. at that point, all devices execute their commands at the same time. using a group command, it is possible, for example, to turn multip le pmbus devices on or off simultaneously. in the case of the adm1278 , it is also possible to issue a power monitor command that initiates a conversion, causing multiple adm1278 devices to sa mple together at the same time. hot swap control com mands operation command the gate pin that drives the fet is controlled by a dedicated hot swa p state machine. the uv and ov input pins, the timer , pwgin , and enable pins, and the current sense all feed into the state machine, and they control when and how strongly the gate is turned off. it is also possible to control the hot swap gate output using commands over the pmbus interface. the operation c ommand can be used to request the hot swap output to turn on. however, if the u v pin indicates that the input supply is less than required, the hot swap output is not turned on, even if the operation command requests that the output be enabled. if the oper ation command is used to disable the hot swap output, the gate pin is held low, even if all hot swap state machine control inputs indicate that it can be enabled. the default state of bit 7 (also named the on bit) of the operation command is 1; therefore, the hot swap output is always enabled when the adm1278 emerges from uvlo. if the on bit is never changed, the uv input or the enable / enable input is the hot swap master on/off control signal. if the on bit is set to 0 while the uv signal is high, the hot swap output is turned off. if the uv signal is low or if the ov signal is high, the hot swap output is already off and the status of the on bit has no effect. if the on bit is s et to 1, the hot swap output is requested to turn on. if the uv signal is low or if the ov signal is high, setting the on bit to 1 has no effect, and the hot swap output remains off. it is possible to determine at any time whether the hot swap output is en abled using the status_byte or the status_word command (see the status commands section). the operation command can also clear any latched faults in the status registers. to clear latched faults, set the on bit to 0 and then reset it to 1. this also clears the latche d fault p in. device_config command the device_config command configures certain settings within the adm1278 , for example, enabling or disabling fet health detection , general - purpose output pin configuration, and modifying the duration of the severe overcurrent settings . power_cycle command the power_cycle command can be used to request that the adm1278 be turned off for approximately five seconds and then turned back on. this command is useful if the processor that controls the adm1278 is also powered off when the adm1278 is turned off. this command allows the processor to request that the adm1278 turn off and on again as part of a single command. adm1278 information commands capability command the capability command ca n be used by host pr ocessors to determine the i 2 c bus features that are supported by the adm1278 . the features that can be reported include the max imum bus speed, whether the device supports the packet error checki ng (pec) byte, and the smbalert reporting function. pmbus_revision command the pmbus_revision command reports the version of part i and part ii of the pmbus standard. mfr_id, mfr_model, and mfr_revision commands the mfr_id, mfr_model, and mfr_revision comm ands return ascii strings that can be used to facilitate detection and identification of the adm1278 on the bus. these commands are read using the smbus block read message type. this message type requires that the adm1278 return a byte count corresponding to the length of the string data that is to be read back. rev. a | page 37 of 61
adm1278 data sheet status commands the adm1278 provides a number of status bits to report faults and warnings from the hot swap controller and the power monitor. these status bits are located in six differe nt registers that are arranged in a hierarchy. the status_byte and status_word commands provide 8 bits and 16 bits of high level information, respectively. the status_byte and status_word commands contain the most important status bits, as well as pointer bits that indicate whether any of the five other status registers need to be read for more detailed status information. in the adm1278 , a particular distinction is made between faults and warnin gs. a fault is always generated by the hot swap controller and is typically defined by hardware component values. events that can generate a fault are ? overcurrent condition that causes the hot swap timer to time out ? overvoltage condition on the ov pin ? unde rvoltage condition on the uv pin ? overtemperature condition ? fet health issue detected when a fault occurs, the hot swap controller always takes some action, usually to turn off the gate pin, which is driving the fet. th e fault p in is asser ted , and the pwrgd pin is deasserted. a fault can also generate an smbalert on the gpo 2/ alert2 pin. all warnings in the adm1278 are generated by the power monitor, which samples the voltage, current, and temperature and then compares these measurements to the threshold values set by the various limit commands. a warning has no effect on the hot swap controller, but it may generate an smbalert on one or both of the gp ox/ alertx output pins. when a status bit is set, it always means that the status condition fault or warning is active or was active at some point in the past. when a fault or warning bit is set, it is latched until it is explicitly cleared using either the operation or the clear_faults command. some other status bits are live, that is, they always reflect a status condition and are never latched. status_byte and status_word commands the status_byte and status_word commands obtain a snapshot of the overall device status. these commands indicate whether it is necessary to read more detailed information using the other status commands. the low byte of the word returned by the status_word command is the same byte returned by the status_byte command. the high byte of the word returned by the status_word command provides a number of bits that determine which of the other status commands needs to be issued to obtain all active status bits. the status bits for fe t health and power good are also found in the high byte of status_word. status_input command the status_input command returns a number of bits relating to voltage faults and warnings on the input supply as well as the overpower warning. status_vout command the status_vout command returns a number of bits relating to voltage warnings on the output supply. status_iout command the status_iout command returns a number of bits relating to current faults and warnings on the output supply. status_temperature comma nd the status_temperature command returns a number of bits relating to temperature faults and warnings at the external transistor. status_mfr_specific command the status_mfr_specific command is a standard pmbus command, but the contents of the byte returne d are specific to the adm1278 . clear_faults command the clear_faults command clear s fault and warnings bits when they are set. fault and warnings bits are latched when they are set. in this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred. if the clear_faults command is issued and the fault or warning condition is no longer active, the status bit is cleared. if the co ndition is still active for example, if an input voltage is below the undervoltage threshold of the uv pin the clear_faults command attempts to clear the status bit, but that status bit is immediately set again. gpo and alert pin se tup commands two multipu rpose pins are provided on the adm1278 : gpo 1/ alert1 / conv and gpo2 / alert2 . these pins can be configured over the pmbus in one of three output modes, as follows : ? g eneral - purpose digital output ? output for generating an smbalert when one or more fault/warning status bits become active in the pmbus status registers ? digital comparator in digital comparator mode, the current, voltage, power and temperature warning thr esholds are compared to the values read or calculated by the adm1278 . the comparison result sets the output high or low according to whether the value is greater or less than the warning thresho ld that has been set. for an example of how to configure these pins to generate an smbalert and how to respond and clear the condition, see the example use of smbus ara section. rev. a | page 38 of 61
data sheet adm1278 alert1_config and alert2_config commands using combinations of bit masks, the alert1_config and alert2_config commands select the status bits that, when set, generate an smbalert sig nal to a processor, or control the digital comparator mode. pin 13 and pin 14 (gpo1 / alert1 / conv and gpo 2/ alert2 ) m ust be configured in smbalert or digital comparator mode in the device_config register. when pin 13 or pi n 14 is configured in gpo mode, the pin is under software control. if this mode is set, the smbalert masking bits are ignored. power monitor comman ds the adm1278 provides a high accuracy, 12 - bit current, voltage , and temperature power monitor. the power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single shot mode with different sample averaging options. the power monitor can me asu re the following quantities: ? input voltage (v in ) ? output voltage (v out ) ? output current (i out ) ? external temperature the following quantities are then calculated: ? input power (p in ) ? input energy (e in ) pmon_config command the power monitor can run in a variety of modes . the pmon_config command set s up the power monitor. the settings that can be configured are as follows: ? single shot or continuous sampling ? v in /v out /temperature sampling enable/disable ? current and voltage sample averaging ? power sample averaging ? simultaneous sampling enable/disable ? temperature sensor filter enable/disable modifying the power monitor settings while the power monitor is sampling is not recommended. to ensure correct operation of the device and to avoid any potential spurious data or the generation of status alerts, stop the power monitor before any of these settings are changed. pmon_control command power monitor sampling can be initiated via hardware or via software using the pmon_control command. this command can be used with singl e shot or continuous mode. read_vin, read_vout, and read_iout commands the adm1278 power monitor always measures the voltage developed across the sense resistor to provide a current measurement. the input v oltage measurement from the hs+ pin is also enabled by default. the output voltage present on the vout pin is available if enabled w ith the pmon_config command. read_temperature_1 command temperature measurement at an external transistor can also be enabled with the pmon_config command. if enabled, the temperature sensor takes over the adc for 64 s (typical) every 6 ms and returns a m easurement every 12 ms. read_pin, read_pin_ext, read_ein, and read_ein_ext commands the 12 - bit input voltage (v in ) and 12 - bit current ( i out ) measure - ment values are multiplied by the adm1278 to give the input power value. this is accomplished by using fixed point arithmetic, and produces a 24 - bit value. it is assumed that the numbers are in the 12.0 format, meaning that there is no fractional part. note that only positive i out values are used to avoid returning a negative power. this 24 - bit value can be read from the adm1278 using the read_pin_ext command, where the most significant bit (msb) is always a zero because pin_ext is a twos c omplement binary value that is always positive. the 16 most significant bits of the 24 - bit value are used as the value for p in . the msb of the 16 - bit p in word is always zero, because p in is a twos complement binary value that is always positive. each time a power calculation is completed, the 24 - bit power value is added to a 24 - bit energy accumulator register. this is a twos complement representation as well; therefore, the msb is always zero. each time this energy accumulator register rolls over from 0x7ff fff to 0x000000, a 16 - bit rollover counter is incre mented. the rollover counter is straight binary, with a maximum value of 0xffff before it rolls over. a 24 - bit straight binary power sample counter is also incremented by 1 each time a power value is calcu lated and added to the energy accumulator. these registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the adm1278 . a bus host can read these values, and by calculating the delta in the energy accumulated, the delta in the number of samples, and the time delta since the last read, the host can calculate the average power since the last read, as well as the energy consumed since then. the time delta is calculated by the bus host based on when it sends its commands to read from the device, and is not provided by the adm1278 . to avoid loss of data, the bus host must read at a rate that ensures the rollover counter does not wrap around more than once, and if the counter does wrap around, that the next value read for p in is less than the previous one. rev. a | page 39 of 61
adm1278 data sheet the read_ein com mand returns the top 16 bits of the energy accumulator, the lower 8 bits of the rollover counter, and the full 24 bits of the sample counter. the read_ein_ext command returns the full 24 bits of the energy accumulator, the full 16 bits of the rollover coun ter, and the full 24 bits of the sample counter. the use of the longer rollover counter means that the time interval between reads of the device can be increased from seconds to minutes without losing any data. peak_iout, peak_vin, peak _ vout, peak _ pin, and peak_temperature commands in addition to the standard pmbus commands for reading voltage and current, the adm1278 provides commands that can report the maximum peak voltage, current, power, or temperature value since the peak value was last cleared. the peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. individual peak values are cleared by writing a 0 value with the corresponding command. warning limit setup commands the adm1278 power monitor can monitor a number of different warning conditions simultaneously and report any current, voltage, power, or temperature values that exceed the user defined thresholds using the status commands. all comparisons performed by the power monitor require the measured value to be strictly greater or less than the threshold value. at power - up, all threshold limits are set to either minimu m scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage, overcurrent, overpower, or overtemperature conditions). this effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values. vin_ov_warn_limit and vin_uv_warn_limit commands the vin_ov_warn_limit and vin_uv_warn_limit commands set the ov and uv thresholds on the input voltage, as measured at the hs+ pin. vout_ ov_warn_limit and vout_uv_warn_limit commands the vout_ov_warn_limit and vout_uv_warn_ limit commands set the ov and uv thresholds on the output voltage, as measured at the vout pin. iout_oc_warn_limit command the iout_oc_warn_limit command sets the oc threshold for the current flowing through the sense resistor. ot_warn_limit command the ot_warn_limit command set s the overtemperature threshold for the temperature measured at the external transistor. pin_op_warn_limit command the pin_op_warn_limit comman d set s the overpower threshold for the power delivered to the load. pmbus direct format conversion the adm1278 uses the pmbus direct format to represent real - world quantities such as voltage, current, and power values. a direct format number takes the form of a 2 - byte, twos compl ement, binary integer value. it is possible to convert between direct format value and real - world quantities using the following equations. equation 1 converts from real - world quantities to pmbus direct values, and equation 2 converts pmbus direct format values to real - world values. y = ( mx + b ) 10 r (1) x = 1/ m ( y 10 ?r ? b ) (2) where: y is the value in pmbus direct format. x is the real - world value. m is the slope coefficient, a 2 - byte, twos complement integer. b is the offset, a 2 - byte, twos complement integer. r is a scaling exponent, a 1 - byte, twos complement integer. the same equa tions are used for voltage, current, power, and temperature conversions, the only difference being the values of the m, b, and r coefficients that are used. table 12 lists all the coefficients required for the adm1278 . the current and power coefficients shown are dependent on the value of the external sense resistor used in a given application . this means that an additional calculation must be performed to take the sense resistor value into account to obtain the coefficients for a specific sense resistor value. the sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. the m coefficients are defined as 2 - byte , twos complement numbers in the pmbus standard; therefore, the maximum positive value that can be represented is 32,767. if the m value is greater than that, and is to be stored in pmbus stan dard form, then divide the m coefficients by 10, and increase the r coefficient by a value of 1. for example, if a 10 m? sense resistor is used, the m coefficient for power is 6123, and the r coefficient is ?1. example 1: iout_oc_warn_limit requires a curr ent - limit value expressed in direct format. if the required current limit is 10 a and the sense resistor is 2 m, the first step is to determine the voltage coefficient. this is simply m = 800 2, giving 1600. rev. a | page 40 of 61
data sheet adm1278 using equation 1, and expressing x, in units of amperes, y = ((1600 10) + 20,475) 10 ?1 y = 3647.5 = 3648 (rounded up to integer form) writing a value of 3648 with the iout_oc_warn_limit command sets an overcurrent warning at 10 a. example 2: the read_iout command returns a direct format value of 3339 representing the current flowing th rough a sense resistor of 1 m?. to convert this value to the current flowing, use equation 2, with m = 800 1. x = 1/800 (3339 10 1 ? 20,475) x = 16.14 a this means that, when read_iout returns a value of 3339, 16.14 a is flowing in the sense resistor. note that the same calculations that are used to convert power values also apply to the energy accumulator value returned by the read_ein command because the energy accumulator is a summ ation of multiple power valu es. the read_pin_ext and read_ein_ext commands return 24- bit extended precision versions of the 16 - bit values returned by read_pin and read_ein. the direct format values must be divided by 256 prior to being converted with the coefficients shown in table 12. example 3: the pin_op_warn_limit command requires a power limit va lue expressed in direct format. if the required power limit is 350 w and the sense resistor is 1 m, the first step is to determine the m coefficient, that is, m = 6123 1, which is 6123. using equation 1, y = ((6123 350) 10 ?2 y = 21,430.5 = 21,431 (rounded up to integer form) writing a value of 21,431 with the pin_op_warn_limit co mmand sets an overpower warning at 350 w. voltage and current conversion using lsb values the direct format voltage and current values returned by the read_vin, read_vout, and read_iout commands and the corresponding peak versions are the data output direc tly by the adm1278 adc. because the voltages and currents are 12 - bit adc ou tput codes, they can also be converted to real - world values when there is knowledge of the size of the l sb on the adc. the m, b, and r coefficients defined for the pmbus conversion are required to be whole integers by the standard and have, therefore, been rounded slightly. using this alternative method, with the exact lsb values, can provide somewhat more accurate numeric al conversions. to convert an adc code to current in amperes, use the following formulas: v sense_mo = lsb current ( i adc ? 2048) i out = v sense_mo /( r sense 0.001) where: v sense_mo = (v mo+ ) ? (v mo? ). lsb current = 12.51 v. i adc is the 12 - bit adc code. i out is the measured current value in amperes. r sense is the value of the sense resistor in milliohms. to convert an adc code to a voltage, use the following formula: v m = lsb voltage ( v adc + 0.5) where: v m is the measured value in volts. lsb voltage = 5.104 mv . v adc is the 12 - bit adc code. to convert a current in amperes to a 12 - bit value, use the following formula (round the result to the nearest integer): v sense_mo = i a r sense 0.001 i code = 2048 + ( v sense_mo / lsb current ) where: v sense_mo = (v mo+ ) ? (v mo? ). i a is the current value in amperes. r sense is the value of the sense resistor in milliohms. i code is the 12 - bit adc code. lsb current = 12.51 v. to convert a voltage to a 12 - bit value, the following formula can be used (round the result to the nearest int eger): v code = ( v a / lsb voltage ) ? 0.5 where: v code is the 12 - bit adc code. v a is the voltage value in volts. lsb voltage = 5.104 mv. table 12 . pmbus conversion to real - world coefficients coefficient voltage (v) current (a) power (w) temperature (c) m + 19,599 + 800 r sense + 6123 r sense + 42 b 0 + 20,475 0 + 31,880 r ?2 ?1 ?2 ?1 rev. a | page 41 of 61
adm1278 data sheet alert pin behavior the adm1278 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. faults and warnings a pmbus fault on the adm1278 is typically generated due to an analog event (the exception being a temperature fault) and causes a change in state in the hot swap output, turning it off. the defined fault sources are as follows: ? undervoltage (uv) event detected on the uv pin. ? overvoltage (ov) event detected on the ov pin. ? overcurrent (oc) event that causes a hot swap timeout. ? overtemperature (ot) event detected at the external transistor. ? fault detected with the pass mosfet. fault s are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. when a fault occurs, a corresponding status bit is set in one or more status_xxx registers. a value of 1 in a status register bit field always indicates a fault or warning condition. fault and warning bits in the status registers are latched when set to 1. to clear a latched bit to 0 provided that the fault condition is no longer active use the clear_faults command or use the operation command to turn the hot swap output off and then on again. a warning is less severe than a fault and never causes a change in the state of the hot swap controller. the sources of a warning are defined as follows: ? cml: a communications error occurred on the i 2 c bus. ? hs_inlim_f ault: the circuit breaker threshold was tripped and the timer pin started ramping, but did not necessarily shut the system down. ? i out oc warning from the adc. ? v in uv warning from the adc. ? v in ov warning from the adc. ? v out uv warning from the adc. ? v out ov w arning from the adc. ? p in overpower (op) warning from the v in i out calculation. ? ot warning from the adc. ? hysteretic output warning from the adc. generating an alert a host device can periodically poll the adm1278 using the status commands to determine whether a fault/warning is active. however, this polling is very inefficient in terms of software and processor resources. the adm1278 has two output pins (gp o1/ alert1 /co nv and gp o2/ alert2 ) that can be used to generate inter rupts to a host processor. by default at power - up, the open - drain gpo 1/ alert1 /c onv and gpo 2/ alert 2 outp uts are high impedance; therefore, the pins can be pulled high through a resistor. the gpo 1/ alert1 / conv and gpo 2/ alert2 p ins are disabled by default on the adm1278 . any one or more of the faults and warnings listed in the faults and warnings section can be enabled and cause an alert, making the corresponding gpo 1/ alert1 /c onv or gpo2 / alert2 pin active. by default, the active state of the gpo 1/ alert1 / conv and gpo2 / alert2 p ins are low. for example, to use gpo 2/ al ert2 t o monitor the v out uv warning from the adc, the followings steps must be performed: 1. set a threshold level with the vout_uv_warn_limit command. 2. set the vout_uv_warn_en2 bit in the alert2_config register. 3. start the power monitor sampling on v out (e nsure the power monitor is configured to sample v out in the pmon_config register) . if a v out sample is taken that is below the configured v out uv value, the gpo 2/ alert2 p in is pulled low, signaling an interrupt to a processor. handling/clearing an alert when faults/warnings are configured on the gpo1 / alert1 / conv or gpo2 / alert2 p ins, the pin becomes active to signal an interrupt to the processor. (the pin is active low, unless inversion is enabled.) the gpo1 / alert1 / conv or gpo2 / alert2 s ignal performs the functions of an smbalert. note that the gp o1/ alert1 /co nv and gpo 2/ alert2 p ins can become active independently but they are always made inactive together. a processor can respond to the interrupt in one of two ways , depending on whether there is a single or multiple devices on the bus . single device on bus when there is only one device on the bus, the processor simply read s the status bytes and issue s a clear_faults command to clear all the status bits, which causes the deassertion of the g po1/ alert1 /c onv or gpo 2/ alert2 lin e. if there is a pers istent fault (for example, an undervoltage on the input), the status bits remain set after the clear_ faults command is execute d because the fault has not been removed. however, the gpo 1/ alert1 / conv or gpo 2/ alert2 l ine is not pulled low unless a new fault or warning becomes active. if the cause of the smbalert is a power monitor generated warning and the power monitor is running continuously, the next sample gener ates a new smbalert after the clear_faults command is issued. rev. a | page 42 of 61
data sheet adm1278 rev. a | page 43 of 61 multiple devices on bus when there are several devices on the bus, the processor issues an smbus alert response address (ara) command to find out which device asserted the smbalert line. the processor reads the status bytes from that device and issues a clear_faults command. smbus alert response address the smbus ara is a special address that can be used by the bus host to locate any devices that need to communicate with the bus host. a host typically uses a hardware interrupt pin to monitor the smbus alert pins of multiple devices. when the host interrupt occurs, the host issues a message on the bus using the smbus receive byte or receive byte with pec protocol. the special address used by the host is 0x0c. any devices that have an smb alert signal return their own 7-bit address as the seven msbs of the data byte. the lsb value is not used and can be either 1 or 0. the host reads the device address from the received data byte and proceeds to handle the alert condition. more than one device may have an active smbalert signal and attempt to communicate with the host. in this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. the device that succeeds disables its smbus alert signal. if the host sees that the smbus alert signal is still low, it continues to read addresses until all devices that need to communicate have successfully transmitted their addresses. example use of smbus ara the full sequence of steps that occurs when an smbalert is generated and cleared is as follows: 1. a fault or warning is enabled using the alert2_config command, and the corresponding status bit for the fault or warning changes from 0 to 1, indicating that the fault or warning has just become active. 2. the gpo2/ alert2 pin becomes active (set low) to signal that an smbalert is active. 3. the host processor issues an smbus ara command to determine which device has an active alert. 4. if there are no other active alerts from devices with lower i2c addresses, this device makes the gpo2/ alert2 pin inactive (set high) during the no acknowledge bit period after it sends its address to the host processor. 5. if the gpo2/ alert2 pin stays low, the host processor must continue to issue smbus ara commands to devices to determine the addresses of all devices that require a status check. 6. the adm1278 continues to operate with the gpo2/ alert2 pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. that is, if a status bit for a fault/warning that is enabled on the gpo2/ alert2 pin and that was not already active (equal to 1) changes from 0 to 1, a new alert is generated, causing the gpo2/ alert2 pin to become active again. digital comparator mode the gpo1/ alert1 /conv and gpo2/ alert2 pins can be configured to indicate if a user defined threshold for voltage, current, or power is being exceeded. in this mode, the output pin is live and is not latched when a warning threshold is exceeded. in effect, the pin acts as a digital comparator, where the threshold is set using the warning limit threshold commands. the alertx_config command is used, as for the smbalert configuration, to select the specific warning threshold to be monitored. the gpo1/alert1/conv or gpo2/alert2 pin then indicates if the measured value is above or below the threshold. typical application circuits gate q 1 mo+ hs+ hs? timer timer adm1278-1 mo? r sense 4.5v to 20v vcc v cp vcap i sense uv ov 1.0v 1.0v temp vout pwgin 1.0v v out 12-bit adc scl sda adr2 i sense hs+ temp ldo charge pump timeout i out gpo1/alert2 enable gpo2/alert1/conv v cbos istart iset pset timeout current- limit control ref select 1.0v hs? fault retry pwrgd adr1 csout gate drive/ logic logic and pmbus analog vout 50 + + + + ? ? ? ? + ? gnd pgnd 12198-030 figure 71. adm1278-1 typical applic ation circuit
ad m1278 data sheet gate q 1 mo+ hs+ hs? timer timer adm1278-2 mo? r sense 4.5v t o 20v vcc v cp vcap i sense uv ov 1.0v 1.0v temp vout pwgin 1.0v v out 12-bit adc scl sda adr2 i sense hs+ temp ldo charge pump timeout i out gpo2/alert2 enable gpo1/alert1/conv v cbos istart iset pset timeout current- limit control ref select 1.0v hs? fault retry pwrgd mdat mclk spi_ss adr1 gate drive/ logic logic and pmbus spi csout analog vout 50 + + + + ? ? ? ? + ? gnd pgnd 12198-031 figure 72 . adm1278 - 2 typical application circuit gate q 1 mo+ hs+ hs? timer timer adm1278-3 mo? r sense 4.5v t o 20v vcc v cp vcap i sense uv ov 1.0v 1.0v temp vout pwgin 1.0v v out 12-bit adc scl sda adr2 i sense hs+ temp ldo charge pump timeout i out gpo1/alert2 enable gpo2/alert1/conv v cbos istart iset pset timeout current- limit control ref select 1.0v hs? fault retry pwrgd adr1 csout gate drive/ logic logic and pmbus analog vout 50 + + + + ? ? ? ? + ? gnd pgnd 12198-330 figure 73 . adm1278 - 3 typical application circuit rev. a | page 44 of 61
data sheet adm1278 pmb us command reference register addresses are in hexadecimal format. table 13 . pmbus command summary address name smbus transaction type number of data bytes reset 0x01 operation read/write byte 1 0x80 0x03 clear_faults send byte 0 not applicable 0x19 capability read byte 1 0xb0 0x42 vout_ov_warn_limit read/write word 2 0x0fff 0x43 vout_uv_warn_limit read/write word 2 0x0000 0x4a iout_oc_warn_limit read/write word 2 0x0fff 0x4f ot_fault_limit read/write word 2 0x0fff 0x51 ot_warn_limit read/write word 2 0x0fff 0x57 vin_ov_warn_limit read/write word 2 0x0fff 0x58 vin_uv_warn_limit read/write word 2 0x0000 0x6b pin_op_warn_limit read/write word 2 0x7fff 0x78 status_byte read byte 1 0x00 0x79 status_word read word 2 0x0000 0x7a status_vout read byte 1 0x00 0x7b status_iout read byte 1 0x00 0x7c status_input read byte 1 0x00 0x7d status_temperature read byte 1 0x00 0x80 status_mfr_specific read byte 1 0x00 0x86 read_ein block read 6 0x000000000000 0x88 read_vin read word 2 0x0000 0x8b read_vout read word 2 0x0000 0x8c read_iout read word 2 0x0000 0x8d read_temperature_1 read word 2 0x0000 0x97 read_pin read word 2 0x0000 0x98 pmbus_revision read byte 1 0x22 0x99 mfr_id block read 3 ascii = adi 0x9a mfr_model block read 10 ascii = adm1278 -xy 0x9b mfr_revision block read 1 0x33 0x9d mfr_date block read 6 ascii = yymmdd 0xd0 peak_iout read/write word 2 0x0000 0xd1 peak_vin read/write word 2 0x0000 0xd2 peak_vout read/write word 2 0x0000 0xd3 pmon_control read/write byte 1 0x01 0xd4 pmon_config read/write word 2 0x0714 0xd5 alert1_config read/write word 2 0x0000 0xd6 alert2_config read/write word 2 0x0000 0xd7 peak_temperature read/write word 2 0x0000 0xd8 device_config read/write word 2 0x000d 0xd9 power_cycle send byte 0 not applicable 0xda peak_pin read/write word 2 0x0000 0xdb read_pin_ext block read 3 0x000000 0xdc read_ein_ext block read 8 0x0000000000000000 0xf2 hysteresis_low read/write word 2 0x0000 0xf3 hysteresis_high read/write word 2 0xffff 0xf4 status_hysteresis read byte 1 0x00 0xf6 strt_up_iout_lim read/write word 2 0x000f rev. a | page 45 of 61
adm1278 data sheet rev. a | page 46 of 61 register details operation register address: 0x01, reset: 0x80, name: operation this command requests the hot swap turn on and turn off. when turning the hot swap on, it clears status bits for any faults or warnings that are not active. table 14. bit descriptions for operation bits bit name settings description reset access 7 on hot swap enable. 0x1 rw 0 hot swap output disabled. 1 hot swap output enabled. [6:0] reserved always reads as 0000000. 0x00 reserved clear faults register address: 0x03, send byte, no data, name: clear_faults this command clears fault and warning bits in all the status registers. any faults that are still active are not cleared and re main set. any warnings and the ot_fault that are generated by the power monitor are cleared, but may be asserted again if they remain active following the next power monitor conversion cycle. this command does not require any data. pmbus capability register address: 0x19, reset: 0xb0, name: capability allows the host system to determine the smbus interface capabilities of the device. table 15. bit descriptions for capability bits bit name settings description reset access 7 pec_support packet error correction (pec) support. 0x1 r 1 always reads as 1. pec is supported. [6:5] max_bus_speed maximum bus interface speed. 0x1 r 01 always reads as 01. maximum supported bus speed is 400 khz. 4 smbalert_support smbalert support. 0x1 r 1 always reads as 1. device supports smbalert and ara. [3:0] reserved always reads as 0000. 0x0 reserved v out ov warning limit register address: 0x42, reset: 0x0fff, name: vout_ov_warn_limit this register sets the overvoltage warning limit for the voltage measured on the vout pin. table 16. bit descriptions for vout_ov_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] vout_ov_warn_limit overvoltage warning threshold for the vout pin measurement, expressed in direct format. 0xfff rw
data sheet adm1278 rev. a | page 47 of 61 v out uv warning limit register address: 0x43, reset: 0x0000, name: vout_uv_warn_limit this register sets the undervoltage warning limit for the voltage measured on the vout pin. table 17. bit descriptions for vout_uv_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] vout_uv_warn_limit undervoltage warning threshold for the vout pin measurement, expressed in direct format. 0x000 rw i out oc warning limit register address: 0x4a, reset: 0x0fff, name: iout_oc_warn_limit this register sets the overcurrent warning limit for the current measured between the mo+ and the mo? pins. table 18. bit descriptions for iout_oc_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] iout_oc_warn_limit overcurrent warning threshold for the i out measurement, expressed in direct format. 0xfff rw ot fault limit register address: 0x4f, reset: 0x0fff, name: ot_fault_limit this register sets the overtemperature fault limit for the temperature measured on the temp pin. table 19. bit descriptions for ot_fault_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] ot_fault_limit overtemperature fault threshold for the temp pin measurement, expressed in direct format. 0xfff rw ot warning limit register address: 0x51, reset: 0x0fff, name: ot_warn_limit this register sets the overtemperature warning limit for the temperature measured on the temp pin. table 20. bit descriptions for ot_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] ot_warn_limit overtemperature warning threshold for the temp pin measurement, expressed in direct format. 0xfff rw v in ov warning limit register address: 0x57, reset: 0x0fff, name: vin_ov_warn_limit this register sets the overvoltage warning limit for the voltage measured on the hs+ pin. table 21. bit descriptions for vin_ov_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] vin_ov_warn_limit overvoltage warning threshold for the hs+ pin measurement, expressed in direct format. 0xfff rw
adm1278 data sheet rev. a | page 48 of 61 v in uv warning limit register address: 0x58, reset: 0x0000, name: vin_uv_warn_limit this register sets the undervoltage warning limit for the voltage measured on the hs+ pin. table 22. bit descriptions for vin_uv_warn_limit bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] vin_uv_warn_limit undervoltage warning threshold for the hs+ pin measurement, expressed in direct format. 0x000 rw p in op warning limit register address: 0x6b, reset: 0x7fff, name: pin_op_warn_limit this register sets the overpower warning limit for the power calculated based on v in i out . table 23. bit descriptions for pin_op_warn_limit bits bit name settings description reset access 15 reserved always reads as 0. 0x0 reserved [14:0] pin_op_warn_limit overpower warning threshold for the v in i out power calculation, expressed in direct format. 0x7fff rw status byte register address: 0x78, reset: 0x00, name: status_byte provides status information for critical faults and certain top-level status commands in the device. this is also the lower byt e returned by status_word. a bit set to 1 indicates that a fault or warning has occurred. table 24. bit descriptions for status_byte bits bit name settings description reset access 7 reserved always reads as 0. 0x0 reserved 6 hotswap_off hot swap gate is off. this bit is live. 0x0 r 0 the hot swap gate drive output is enabled. 1 the hot swap gate drive output is disabled, and the gate pin is pulled down. this can be due to, for example, an overcurrent fault that causes the device to latch off, an undervoltage condition on the uv pin, or the use of the operation command to turn the output off. 5 reserved always reads as 0. 0x0 reserved 4 iout_oc_fault i out overcurrent fault. this bit is latched. 0x0 r 0 no overcurrent output fault detected. 1 the hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the timer pin has elapsed, causing the hot swap gate drive to shut down. 3 vin_uv_fault v in fault. this bit is latched. 0x0 r 0 no undervoltage input faul t detected on the uv pin. 1 an undervoltage input fault was detected on the uv pin. 2 temp_fault temperature fault or warning. this bit is live. 0x0 r 0 there are no active status bits to be read by status_temperature. 1 there are one or more active status bits to be read by status_temperature. 1 cml_fault cml fault. this bit is latched. 0x0 r 0 no communications error detected on the i 2 c/pmbus interface. 1 an error was detected on the i 2 c/pmbus interface. errors detected include an unsupported command, invalid pec byte, and incorrectly structured message.
data sheet adm1278 rev. a | page 49 of 61 bits bit name settings description reset access 0 noneabove_status none of the above. this bit is live. 0x0 r 0 no other active status bit reported by any other status command. 1 active status bits are waiting to be read by one or more status commands. status word register address: 0x79, reset: 0x0000, name: status_word provides status information for critical faults and all top-level status commands in the device. the lower byte is also returne d by status_byte. table 25. bit descriptions for status_word bits bit name settings description reset access 15 vout_status v out warning. this bit is live. 0x0 r 0 there are no active status bits to be read by the status_vout register. 1 there are one or more active status bits to be read by status_vout. 14 iout_status i out fault or warning. this bit is live. 0x0 r 0 there are no active status bits to be read by the status_iout register. 1 there are one or more active status bits to be read by the status_iout register. 13 input_status input warning. this bit is live. 0x0 r 0 there are no active status bits to be read by the status_input register. 1 there are one or more active status bits to be read by status_input. 12 mfr_status manufacture specific faul t or warning. this bit is live. 0x0 r 0 there are no active status bits to be read by the status_mfr_specific register. 1 there are one or more active status bits to be read by status_mfr_specific register. 11 pgb_status power is not good. this bit is live. 0x0 r 0 output power is good. the voltage on the pwgin pin is above the threshold. 1 output power is bad. the voltage on the pwgin pin is below the threshold. [10:9] reserved 0x0 reserved 8 fet_health_fault fet health faul t. this bit is latched. 0x0 r 0 no fet faults have been detected. 1 a fault condition has been detected on the fet. 7 reserved always set to 0. 0x0 reserved 6 hotswap_off duplicate of corresponding bit in the status_byte register. 0x0 r 5 reserved always set to 0. 0x0 reserved 4 iout_oc_fault duplicate of correspondin g bit in the status_byte register. 0x0 r 3 vin_uv_fault duplicate of corresponding bit in the status_byte register. 0x0 r 2 temp_fault duplicate of corresponding bit in the status_byte register. 0x0 r 1 cml_fault duplicate of corresponding bit in the status_byte register. 0x0 r 0 noneabove_status duplicate of correspond ing bit in the status_byte register. 0x0 r
adm1278 data sheet rev. a | page 50 of 61 v out status register address: 0x7a, reset: 0x00, name: status_vout provides status information for warnings related to v out . table 26. bit descriptions for status_vout bits bit name settings description reset access 7 reserved always reads as 0. 0x0 reserved 6 vout_ov_warn v out overvoltage warning. 0x0 r 0 no overvoltage condition on the output supply detected by the power monitor. 1 an overvoltage condition on the o utput supply was detected by the power monitor. this bit is latched. 5 vout_uv_warn v out uv warning. 0x0 r 0 no undervoltage condition on th e output supply detected by the power monitor. 1 an undervoltage condition on the output supply was detected by the power monitor. this bit is latched. [4:0] reserved always reads as 00000. 0x00 reserved i out status register address: 0x7b, reset: 0x00, name: status_iout provides status information for faults and warnings related to i out . table 27. bit descriptions for status_iout bits bit name settings description reset access 7 iout_oc_fault i out overcurent fault. 0x0 r 0 no overcurrent output fault detected. 1 the hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the timer pin has elapsed, causing the hot swap gate drive to shut down. this bit is latched. 6 reserved always reads as 0. 0x0 reserved 5 iout_oc_warn i out overcurrent warning. 0x0 r 0 no overcurrent condition on the output supply detected by the power monitor using the iout_oc_warn_limit command. 1 an overcurrent condition was detected by the power monitor using the iout_oc_warn_limit command. this bit is latched. [4:0] reserved always reads as 00000. 0x00 reserved input status register address: 0x7c, reset: 0x00, name: status_input provides status information for faults and warnings related to v in and p in . table 28. bit descriptions for status_input bits bit name settings description reset access 7 vin_ov_fault v in overvoltage fault. 0x0 r 0 no overvoltage detected on the ov pin. 1 an overvoltage was detected on the ov pin. this bit is latched. 6 vin_ov_warn v in overvoltage warning fault. 0x0 r 0 no overvoltage condition on the input supply detected by the power monitor. 1 an overvoltage condition on the input supply was detected by the power monitor. this bit is latched.
data sheet adm1278 rev. a | page 51 of 61 bits bit name settings description reset access 5 vin_uv_warn v in undervoltage warning. 0x0 r 0 no undervoltage condition on the in put supply detected by the power monitor. 1 an undervoltage condition on the input supply was detected by the power monitor. this bit is latched. 4 vin_uv_fault v in undervoltage fault. 0x0 r 0 no undervoltage detected on the uv pin. 1 an undervoltage was detected on the uv pin. this bit is latched. [3:1] reserved always reads as 000. 0x0 reserved 0 pin_op_warn p in overpower warning. 0x0 r 0 no overpower condition on the input supply detected by the power monitor. 1 an overpower condition on the input supply was detected by the power monitor. this bit is latched. temperature status register address: 0x7d, reset: 0x00, name: status_temperature provides status information for faults and warnings related to temperature. table 29. bit descriptions for status_temperature bits bit name settings description reset access 7 ot_fault overtemperature fault. 0x0 r 0 no overtemperature fault detected by the adc. 1 an overtemperature fault was detected by the adc. this bit is latched. 6 ot_warning overtemperature warning. 0x0 r 0 no overtemperature warning detected by the adc. 1 an overtemperature warning was detected by the adc. this bit is latched. [5:0] reserved always reads as 000000. 0x0 reserved manufacturer specific status register address: 0x80, reset: 0x00, name: status_mfr_specific provides status information for manufacturer specific faults and warnings. table 30. bit descriptions for status_mfr_specific bits bit name settings description reset access 7 fet_health_fault fet health fault. 0x0 r 0 no fet health problems have been detected. 1 an fet health fault has been detected. this bit is latched. 6 uv_cmp_out uv input comp arator fault output. 0x0 r 0 input voltage to uv pin is above threshold. 1 input voltage to uv pin is below threshold. this bit is live. 5 ov_cmp_out ov input comp arator fault output. 0x0 r 0 input voltage to ov pin is below threshold. 1 input voltage to ov pin is abov e threshold. this bit is live. 4 severe_oc_fault severe overcurrent fault. 0x0 r 0 a severe overcurrent has not been detected by the hot swap. 1 a severe overcurrent has been detected by the hot swap. this bit is latched.
adm1278 data sheet rev. a | page 52 of 61 bits bit name settings description reset access 3 hs_inlim_fault hot swap in limit fault. 0x0 r 0 the hot swap has not actively limited the current into the load. 1 the hot swap has actively limited current into the load. this bit differs from the iout_oc_fault bit in that the hs_inlim_fault bit is set immediately, whereas the iout_oc_fault bit is not set unless the time limit set by the capacitor on the timer pin elapses. this bit is latched. [2:0] hs_shutdown_cause cause of last hot swap shutdown. th is bit is latched until the status registers are cleared. 0x0 r 000 the hot swap is either enabled and working correctly, or has been shut down using the operation command. 001 an ot_fault condition occurred that caused the hot swap to shut down. 010 an iout_oc_fault condition occurred that caused the hot swap to shut down. 011 an fet_health_fault condition occurred that caused the hot swap to shut down. 100 a vin_uv_fault condition occurred that caused the hot swap to shut down. 110 a vin_ov_fault condition occurred that caused the hot swap to shut down. read e in register address: 0x86, reset: 0x000000000000, name: read_ein read the energy metering registers in a single operation to ensure time consistent data. table 31. bit descriptions for read_ein bits bit name settings description reset access [47:24] sample_count this is the total number of p in samples acquired and accumulated in the energy count accumulator. this is an unsigned 24-bit binary value. byte 5 is the high byte, byte 4 is the middle byte, and byte 3 is the low byte. 0x000000 r [23:16] rollover_count number of times that the energy count has rolled over from 0x7fff to 0x0000. this is an unsigned 8-bit binary value. 0x00 r [15:0] energy_count energy accumulator value in pmbus direct format. byte 1 is the high byte, and byte 0 is the low byte. internally, the energy accumulator is a 24-bit value, but only the most signif icant 16 bits are returned with this command. use the read_ein_ext register to access the nontruncated version. 0x0000 r read v in register address: 0x88, reset: 0x0000, name: read_vin reads the input voltage, v in , from the device. table 32. bit descriptions for read_vin bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] read_vin input voltage from the hs+ pin measurement after averaging, expressed in direct format. 0x000 r
data sheet adm1278 rev. a | page 53 of 61 read v out register address: 0x8b, reset: 0x0000, name: read_vout reads the output voltage, v out , from the device. table 33. bit descriptions for read_vout bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] read_vout input voltage from the vout pin measurement after averaging, expressed in direct format. 0x000 r read i out register address: 0x8c, reset: 0x0000, name: read_iout reads the output current, i out , from the device. table 34. bit descriptions for read_iout bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] read_iout output current derived from mo+/mo? sense pin voltage measurement after averaging, expressed in direct format. 0x000 r read temperature 1 register address: 0x8d, reset: 0x0000, name: read_temperature_1 reads the temperature measured by the device. table 35. bit descriptions for read_temperature_1 bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] read_temperature_1 temperature from the temp pin measurement after averaging, expressed in direct format. 0x000 r read p in register address: 0x97, reset: 0x0000, name: read_pin reads the calculated input power, p in , from the device. table 36. bit descriptions for read_pin bits bit name settings description reset access [15:0] read_pin input power calculation, using v in i out , after averaging, expressed in pmbus direct format. p in values are calculated for each v in i out sample, all p in values are then averaged before the value is returned to the read_pin register. 0x0000 r pmbus revision register address: 0x98, reset: 0x22, name: pmbus_revision allows the system to read the pmbus revision that the device supports. table 37. bit descriptions for pmbus_revision bits bit name settings description reset access [7:4] pmbus_p1_revision pmbus part i support. 0x2 r 0010 revision 1.2. [3:0] pmbus_p2_revision pmbus part ii support. 0x2 r 0010 revision 1.2.
adm1278 data sheet rev. a | page 54 of 61 manufacturer id register address: 0x99, reset: ascii = adi, name: mfr_id returns a string identifying the manufacturer of the device. table 38. bit descriptions for mfr_id bits bit name settings description reset access [23:0] mfr_id string identifying manufa cturer as analog devices (adi). 0x494441 r manufacturer model register address: 0x9a, reset: ascii = adm1278-xy, name: mfr_model returns a string identifying the specific model of the device. table 39. bit descriptions for mfr_model bits bit name settings description reset access [79:0] mfr_model string identifying model as adm1278-xy, where xy identifies the particular model type. note that the adm1278-1aa model is identified as adm1278-1a in the mfr_model register. 0x41312d383732314d4441 r manufacturer revision register address: 0x9b, reset: 0x33, name: mfr_revision returns a string identifying the hardware revision of the device. table 40. bit descriptions for mfr_revision bits bit name settings description reset access [7:0] mfr_revision string identifying hardware revision as, for example, 3. 0x33 r manufacturer date register address: 0x9d, reset: ascii = yymmdd, name: mfr_date returns a string identifying the production test date of the device. table 41. bit descriptions for mfr_date bits bit name settings description reset access [47:0] date string identifying test date, in the form of yymmdd. 0x313338303231 r peak i out register address: 0xd0, reset: 0x0000, name: peak_iout reports the peak output current, i out . writing 0x0000 with this command resets the peak value. table 42. bit descriptions for peak_iout bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] peak_iout peak output current measurement, i out , expressed in direct format. 0x000 r
data sheet adm1278 rev. a | page 55 of 61 peak v in register address: 0xd1, reset: 0x0000, name: peak_vin reports the peak input voltage, v in . writing 0x0000 with this command resets the peak value. table 43. bit descriptions for peak_vin bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] peak_vin peak input voltage measurement, v in , expressed in direct format. 0x000 r peak v out register address: 0xd2, reset: 0x0000, name: peak_vout reports the peak output voltage, v out . writing 0x0000 with this command resets the peak value. table 44. bit descriptions for peak_vout bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] peak_vout peak output voltage measurement, v out , expressed in direct format. 0x000 r power monitor control register address: 0xd3, reset: 0x01, name: pmon_control this command starts and stops the power monitor. table 45. bit descriptions for pmon_control bits bit name settings description reset access [7:1] reserved always reads as 0000000. 0x00 reserved 0 convert conversion enable. 0x1 rw 0 power monitor is not running. 1 power monitor is sampling. default. in single shot mode, this bit clears itself after one complete cycle. in continuous mode, this bit must be written to 0 to stop sampling. a rising edge on the conversion input (conv function of pin 13) or a falling edge on spi_ss sets this bit to 1. during sampling, additional conversion edges on these pins are ignored. power monitor configuration register address: 0xd4, reset: 0x0714, name: pmon_config this command configures the power monitor. different combinations of channels can be included in the rotational sampling, and averaging can be set for different measurements. table 46. bit descriptions for pmon_config bits bit name settings description reset access 15 tsfilt temperature sensor filter enable. 0x0 rw 0 disabled. 1 enabled. data sheet specifications are with the temperature sensor filter disabled. 14 simultaneous simultaneous sampling. 0x0 rw 0 disabled. 1 enabled. power monitoring accuracy is reduced. data sheet specifications are with simultaneous sampling disabled.
adm1278 data sheet rev. a | page 56 of 61 bits bit name settings description reset access [13:11] pwr_avg p in averaging. 0x0 rw 000 disables sample averaging for power. 001 sets sample averaging for power to two samples. 010 sets sample averaging for power to four samples. 011 sets sample averaging for power to eight samples. 100 sets sample averaging for power to 16 samples. 101 sets sample averaging for power to 32 samples. 110 sets sample averaging for power to 64 samples. 111 sets sample averaging for power to 128 samples. [10:8] vi_avg v in /v out /i out averaging. 0x7 rw 000 disables sample averaging for current and voltage. 001 sets sample averaging for current and voltage to two samples. 010 sets sample averaging for current and voltage to four samples. 011 sets sample averaging for current and voltage to eight samples. 100 sets sample averaging for current and voltage to 16 samples. 101 sets sample averaging for current and voltage to 32 samples. 110 sets sample averaging for current and voltage to 64 samples. 111 sets sample averaging for current and voltage to 128 samples. [7:5] reserved always reads as 000. 0x0 reserved 4 pmon_mode conversion mode. 0x1 rw 0 single shot sampling. 1 continuous sampling. 3 temp1_en enable temperature sampling. 0x0 rw 0 temperature sampling disabled. 1 temperature sampling enabled. 2 vin_en enable v in sampling. 0x1 rw 0 v in sampling disabled. 1 v in sampling enabled. 1 vout_en enable v out sampling. 0x0 rw 0 v out sampling disabled. 1 v out sampling enabled. 0 reserved always reads as 0. 0x0 reserved alert 1 configuration register address: 0xd5, reset: 0x0000, name: alert1_config this commands allows different combinations of faults and warnings to be configured on the gpo1 output of the gpo1/ alert1 / conv pin. the pin can operate in different modes, configured using the device_config command. table 47. bit descriptions for alert1_config bits bit name settings description reset access 15 fet_health_fault_en1 fet he alth fault enable. 0x0 rw 14 iout_oc_fault_en1 i out overcurrent fault enable. 0x0 rw 13 vin_ov_fault_en1 v in overvoltage fault enable. 0x0 rw 12 vin_uv_fault_en1 v in undervoltage fault enable. 0x0 rw 11 cml_error_en1 communications error enable. 0x0 rw 10 iout_oc_warn_en1 i out overcurrent warning enable. 0x0 rw 9 hysteretic_en1 hysteretic output enable. 0x0 rw 8 vin_ov_warn_en1 v in overvoltage warning enable. 0x0 rw 7 vin_uv_warn_en1 v in undervoltage warning enable. 0x0 rw 6 vout_ov_warn_en1 v out overvoltage warning enable. 0x0 rw 5 vout_uv_warn_en1 v out undervoltage warning enable. 0x0 rw 4 hs_inlim_en1 hot swap in-limit enable. 0x0 rw
data sheet adm1278 rev. a | page 57 of 61 bits bit name settings description reset access 3 pin_op_warn_en1 p in overpower warning enable. 0x0 rw 2 ot_fault_en1 overtemperature fault enable. 0x0 rw 1 ot_warn_en1 overtemperature warning enable. 0x0 rw 0 reserved always reads as 0. 0x0 reserved alert 2 configuration register address: 0xd6, reset: 0x0000, name: alert2_config this commands allows different combinations of faults and warnings to be configured on the gpo2 output of the gpo2/ alert2 pin. the pin can operate in different modes, configured using the device_config command. table 48. bit descriptions for alert2_config bits bit name settings description reset access 15 fet_health_fault_en2 fet he alth fault enable. 0x0 rw 14 iout_oc_fault_en2 i out overcurrent fault enable. 0x0 rw 13 vin_ov_fault_en2 v in overvoltage fault enable. 0x0 rw 12 vin_uv_fault_en2 v in undervoltage fault enable. 0x0 rw 11 cml_error_en2 communications error enable. 0x0 rw 10 iout_oc_warn_en2 i out overcurrent warning enable. 0x0 rw 9 hysteretic_en2 hysteretic output enable. 0x0 rw 8 vin_ov_warn_en2 v in overvoltage warning enable. 0x0 rw 7 vin_uv_warn_en2 v in undervoltage warning enable. 0x0 rw 6 vout_ov_warn_en2 v out overvoltage warning enable. 0x0 rw 5 vout_uv_warn_en2 v out undervoltage warning enable. 0x0 rw 4 hs_inlim_en2 hot swap in-limit enable. 0x0 rw 3 pin_op_warn_en2 p in overpower warning enable. 0x0 rw 2 ot_fault_en2 overtemperature fault enable. 0x0 rw 1 ot_warn_en2 overtemperature warning enable. 0x0 rw 0 reserved always reads as 0. 0x0 reserved peak temperature register address: 0xd7, reset: 0x0000, name: peak_temperature reports the peak measured temperature. writing 0x0000 with this command resets the peak value. table 49. bit descriptions for peak_temperature bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved [11:0] peak_temperature peak temperature meas urement, expressed in direct format. 0x000 r device configuration register address: 0xd8, reset: 0x000d, name: device_config this command configures the hot swap overcurrent threshold and filtering, and gpo1/gpo2 output modes. note that dual function p in names are referenced by the relevant function only, for example, gpo2 for the general-purpose output function of the gpo2/ alert2 pin (see the pin configurations and function descriptions section for full pin mnemonics and descriptions). table 50. bit descriptions for device_config bits bit name settings description reset access [15:12] reserved always reads as 0000. 0x0 reserved 11 fhdis fet health disable. 0x0 rw 0 fet health checks enabled. 1 fet health checks disabled.
adm1278 data sheet rev. a | page 58 of 61 bits bit name settings description reset access 10 pwr_hyst_en when enabled, the general-purpose output alert hysteresis functions refer to power rather than current. the hysteretic_enx bit also needs to be set in alert_config. 0x0 rw 0 current hysteresis mode. 1 power hysteresis mode. [9:8] gpo2_mode gpo2 configuration mode. 0x0 rw 00 default. gpo2 is configured to generate smbalerts. 01 gpo2 can be used as a general-purpose digital output pin. use the gpo2_invert bit to change the output state. 10 reserved. 11 this is digital comparator mode. th e output pin now reflects the live status of the warning or fault bit sele cted for the output. in effect, this is a nonlatched smbalert. 7 gpo2_invert gpo2 invert mode. 0x0 rw 0 in smbalert mode, the output is not inverted, and active low. in gpo mode, the output is set low. 1 in smbalert mode, the output is inverted, and active high. in gpo mode, the output is set high. [6:5] gpo1_mode gpo1 configuration mode. 0x0 rw 00 default. gpo1 is configured to generate smbalerts. 01 gpo1 can be used as a general-purpose digital output pin. use the gpo1_invert bit to change the output state. 10 gpo1 is configured as a convert (conv) input pin. 11 this is digital comparator mode. th e output pin now reflects the live status of the warning or fault bit sele cted for the output. in effect, this is a nonlatched smbalert. 4 gpo1_invert gpo1 invert mode. 0x0 rw 0 in smbalert mode, the output is not inverted, and active low. in gpo mode, the output is set low. 1 in smbalert mode, the output is inverted, and active high. in gpo mode, the output is set high. [3:2] oc_trip_select severe overcurrent threshold select. 0x11 rw 00 125%. 01 150%. 10 200%. 11 default, 225%. 1 oc_retry_dis severe oc retry mode. 0x0 rw 0 retry once immediately after severe overcurrent event. 1 latch off after severe overcurrent event. 0 oc_filt_select severe overcurrent filter select. 0x1 rw 0 200 ns. 1 default, 900 ns. power cycle register address: 0xd9, send byte, no data, name: power_cycle this command is provided to allow a processor to request the hot swap to turn off and turn back on again approximately five sec onds later. this is useful in the event that the hot swap output is powering the processor. this command does not require any data.
data sheet adm1278 rev. a | page 59 of 61 peak p in register address: 0xda, reset: 0x0000, name: peak_pin reports the peak input power, p in . writing 0x0000 with this command resets the peak value. table 51. bit descriptions for peak_pin bits bit name settings description reset access [15:0] peak_pin peak input power calculation, p in , expressed in direct format. 0x0000 r read p in (extended) register address: 0xdb, reset: 0x000000, name: read_pin_ext reads the extended precision version of the calculated input power, p in , from the device. table 52. bit descriptions for read_pin_ext bits bit name settings description reset access [23:0] read_pin_ext extended precision version of peak input power calculation, p in , expressed in pmbus direct format. 0x000000 r read e in (extended) register address: 0xdc, reset: 0x0000000000000000, name: read_ein_ext read the extended precision energy metering registers in a single operation to ensure time consistent data. table 53. bit descriptions for read_ein_ext bits bit name settings description reset access [63:40] sample_count this is the total number of p in samples acquired and accumulated in the energy count accumulator. this is an unsigned 24-bit binary value. byte 7 is the high byte, byte 6 is the middle byte, and byte 5 is the low byte. 0x000000 r [39:24] rollover_ext number of times that the energy count has rolled over from 0x7fffff to 0x000000. this is an unsigned 16-bit binary value. byte 4 is the high byte, and byte 3 is the low byte. 0x0000 r [23:0] energy_ext extended precision energy accumula tor value in pmbus direct format. byte 2 is the high byte, byte 1 is the middle byte, and byte 0 is the low byte. 0x000000 r hysteresis low level register address: 0xf2, reset: 0x0000, name: hysteresis_low this sets the lower threshold used to generate the hysteretic output signal, which can be made available on a general-purpose o utput pin. table 54. bit descriptions for hysteresis_low bits bit name settings description reset access [15:0] hysteresis_low value setting the lower hyster esis threshold, expressed in direct format. 0x000 rw hysteresis high level register address: 0xf3, reset: 0xffff, name: hysteresis_high this sets the higher threshold used to generate the hysteretic output signal, which can be made available on a general-purpose output pin. table 55. bit descriptions for hysteresis_high bits bit name settings description reset access [15:0] hysteresis_high value setting the higher hyster esis threshold, expressed in direct format. 0xffff rw
adm1278 data sheet rev. a | page 60 of 61 hysteresis status register address: 0xf4, reset: 0x00, name: status_hysteresis this status register reports whether the hysteretic comparison is above or below the user defined thresholds, and the iout_oc_warning status bit as well. table 56. bit descriptions for status_hysteresis bits bit name settings description reset access [7:4] reserved always reads as 0000. 0x0 reserved 3 iout_oc_warn i out overcurrent warning. 0x0 r 0 no overcurrent condition on the output supply detected by the power monitor using the iout_oc_warn_limit command. 1 an overcurrent condition was detected by the power monitor using the iout_oc_warn_limit command. 2 hyst_state hysteretic comparison output. 0x0 r 0 comparison output low. 1 comparison output high. 1 hyst_gt_high hysteretic upper threshold comparison. 0x0 r 0 compared value is below upper threshold. 1 compared value is above upper threshold. 0 hyst_lt_low hysteretic lower threshold comparison. 0x0 r 0 compared value is above lower threshold. 1 compared value is below lower threshold. start-up i out limit register address: 0xf6, reset: 0x000f, name: strt_up_iout_lim this sets the current limit initially used while the hot swap is turning on the fet. table 57. bit descriptions for strt_up_iout_lim bits bit name settings description reset access [15:4] reserved always reads as 0x00. 0x00 reserved [3:0] strt_up_iout_lim current limit used during startup, expressed in direct format. 0xf rw
data sheet adm1278 outline dimensions 05-24-2012- a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or se a ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 3.45 3.30 sq 3.15 compliant to jedec standards mo-220- whhd . 3.50 ref figure 74 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adm1278 - 1aacpz ?40c to +85c 32- lead l ead frame chip scale package [l fcsp_wq ] cp -32-13 adm1278 - 1acpz ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 1acpz -rl ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 1bcpz ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 1bcpz -rl ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 2acpz ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 2acpz -rl ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 3acpz ?40c to +85c 32- lead lead frame chip scale package [ lfcsp_wq ] cp -32-13 adm1278 - 3acpz - rl ?40c to +85c 32 - lead lead frame chip scale package [ lfcsp_wq ] cp - 32 - 13 eval - adm1278ebz evaluation kit 1 z = rohs compliant part. ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12198 - 0- 12/14(a) rev. a | page 61 of 61

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